There is no information about PCIe lane configurations.
Presumably it is 1 lane x8.
Is it possible to have 4 lanes each x2
On the product brief, the following layout for PCIe lanes is given.
It shows the PCIe slot is x8 only, but also the PCIe switch only has an x8 connection to the CPU which shared with the SSD, wifi/BT, and USB ports. I haven’t found anything on configuring a specific lane allocation for each PCIe connection to the switch. Also, the schematics show the same PCIe layout.
Hello Oliver
We are working on an embedded application with FU740-C000.
The HiFive Unmatched will be a starting point, but we have to optimize it and reduce cost.
Based on this link, the PCIe controller is an IP from Synopsys
[v4,4/6] dt-bindings: PCI: Add SiFive FU740 PCIe host controller - Patchwork (kernel.org)
SiFive FU740 PCIe host controller is based on the Synopsys DesignWare PCI core.
Next step will be to get the datasheet/SW application manuals from Synopsys
and understand the configuration registers.
If anybody could have experience with this PCI core, please share with us.
If you are asking about PCIe bifurcation, I think I saw a comment somewhere that said it wasn’t supported. I don’t know anything about PCIe myself. I don’t know if this is missing hardware support or missing firmware support or missing driver support or what.
Thank you, Jim,
Looks like this is the definition of configuration we are asking for.
At this time the Synopsys’ PCIe “IP datasheet” is the origin of information.
Will create account to the Synopsys’s support and will request the datasheet.
Also will ask the SiFive’s support to confirm the exact IP reference number.
I had asked if the PCIE port supported bifurcation and got someone replying to the effect that probably nobody had written (driver) support for it so no.
Thank you
The driver is software, so it could be updated.
The IP hardware from Synopsys is hardware and if there is no bifurcation possible this mean NO
I have this document from Synopsys
dwc_pcie_csds.pdf
PCI Express Complete Solution from Synopsys
On page 3 there is a following description:
" PIPE bifurcation as well as PHY macro aggregation for x1 to x16 PHY configurations"
How we could contact a technical support from SuFuve to confirm this functionality in FU740