loquat
July 28, 2018, 3:42am
1
I am developing for HiFive Unleashed borad.
I am developing my original RTOS.
I want to run independently per COREs.
So that I want none coherent cache mode.
Ex. On ARM processor, cache shareble or nonshareble setting.
How to set cache coherent or none coherent?
terpstra
(Wesley W. Terpstra)
July 28, 2018, 4:23am
2
Why do you want non-coherent memory? Just run the programs on non-overlapping memory and they will not share the memory.
loquat
July 29, 2018, 2:04am
3
Ithink,
Overhead available on coherent memory against non-coherent memory.
It’s nothing?
bruce
(Bruce Hoult)
July 29, 2018, 2:16am
4
If only one processor is accessing some address range then that address range can not find itself in the cache of any other processor, and thus there is no overhead.