FreedomStudio FESPI_WRITE_REG error

Hi, everyone!
When I use FreedomStudio debug sample code “global_interrupts”, the following error occurs:

Open On-Chip Debugger 0.10.0+dev-g2c183e3-dirty (2018-01-03-10:25)
Licensed under GNU GPL v2
For bug reports, read
adapter speed: 10000 kHz
Info : auto-selecting first available session transport “jtag”. To override use 'transport select '.
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 10000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0x20000913 (mfg: 0x489 (SiFive, Inc.), part: 0x0000, ver: 0x2)
Info : dtmcontrol_idle=5, dmi_busy_delay=1, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=2, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=3, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=4, ac_busy_delay=0
Info : Disabling abstract command reads from CSRs.
Info : Disabling abstract command writes to CSRs.
Info : [0] Found 2 triggers
Info : Examined RISC-V core; found 1 harts
Info : hart 0: XLEN=32, 2 triggers
Info : Listening on port 3333 for gdb connections
Error: FESPI_WRITE_REG error
Error: auto_probe failed

I do not know how to solve this problem, Can you help me to solve it?

Are you sure you are using a project targeting the right platform? For example, if you are using the HiFive1, did you import the HiFive1 projects?

(The FESPI_WRITE_REG error makes it look like you’re pointint to the wrong openocd.cfg file, because it’s pointing to the wrong place for the flash bank command.)

Thanks for your reply!

I fix some FPGA configuration files of Freedom code and generate bit file, then put on Nexys4 DDR.

On the basis of this, I import the E31 Arty projects, and I fix the expected-id of .cfg file.

I don’t fix flash bank comand. I think Nexys4 DDR and Arty board flash bank should be same.If there should be fix with flash bank, can you give some suggestion, I don’t know how to fix it.