Elf upload error “fespi_write_reg() error writing 0x1 to 0x10014050”

Archive Freedom E300
1

I use a Digilent Arty A7-35T Artix-7 Xilinx FPGA with an Olimex ARM-USB-TINY-H JTAG debugger. The RISC V CPU core has been transmitted on the board, but an error occurred when I tried to upload the “hello” program elf which was found in freedom-e-sdk.

I followed this instruction and I was stuck at the last step.

The openocd tells me the error and the openocd.cfg file has been checked, I didn’t find anything suspicious.

Open On-Chip Debugger 0.10.0+dev (SiFive OpenOCD 0.10.0-2019.08.2)
Licensed under GNU GPL v2
For bug reports:
	https://github.com/sifive/freedom-tools/issues
adapter speed: 10000 kHz
Using JTAG
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 10000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0x20000913 (mfg: 0x489 (SiFive Inc), part: 0x0000, ver: 0x2)
Info : datacount=1 progbufsize=2
Info : Disabling abstract command reads from CSRs.
Info : Examined RISC-V core; found 1 harts
Info :  hart 0: XLEN=32, misa=0x40001104
Info : Listening on port 3333 for gdb connections
Error: fespi_write_reg() error writing 0x1 to 0x10014050
Error: auto_probe failed

Remote communication error.  Target disconnected.: Connection reset by peer.
"monitor" command not supported by this target.
"monitor" command not supported by this target.
You can't do that when your target is `exec'
"monitor" command not supported by this target.
"monitor" command not supported by this target.

openocd.cfg:

#write_config_file
#JTAG adapter setup
adapter_khz     10000

interface ftdi
ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
ftdi_vid_pid 0x15ba 0x002a

ftdi_layout_init 0x0808 0x0a1b
ftdi_layout_signal nSRST -oe 0x0200
ftdi_layout_signal LED -data 0x0800

set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1

flash bank spi0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10014000
init
if {[ info exists pulse_srst]} {
	ftdi_set_signal nSRST 0
	ftdi_set_signal nSRST z
sleep 1500
}
halt

flash protect 0 64 last off
echo "Ready for Remote Connections"