GDB connect failed

Archive Freedom E300
1

When I run demo on FreedomStudio, there occur error as follow:

Open On-Chip Debugger 0.10.0+dev-00161-g6c719f0-dirty (2018-04-10-23:16)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
adapter speed: 10000 kHz
Info : auto-selecting first available session transport “jtag”. To override use 'transport select ‘.
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 10000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0x20000913 (mfg: 0x489 (SiFive, Inc.), part: 0x0000, ver: 0x2)
Info : dtmcontrol_idle=5, dmi_busy_delay=1, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=2, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=3, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=4, ac_busy_delay=0
Info : Disabling abstract command reads from CSRs.
Info : Disabling abstract command writes to CSRs.
Info : [0] Found 2 triggers
Info : Examined RISC-V core; found 1 harts
Info : hart 0: XLEN=32, 2 triggers
Info : Listening on port 3333 for gdb connections
Info : JTAG tap: riscv.cpu tap/device found: 0x20000913 (mfg: 0x489 (SiFive, Inc.), part: 0x0000, ver: 0x2)
Info : dtmcontrol_idle=5, dmi_busy_delay=5, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=6, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=7, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=8, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=9, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=10, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=12, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=14, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=16, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=18, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=20, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=23, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=26, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=29, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=32, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=36, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=40, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=45, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=50, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=56, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=62, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=69, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=76, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=84, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=93, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=103, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=114, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=126, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=139, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=153, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=169, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=186, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=205, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=226, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=249, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=274, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=302, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=333, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=367, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=404, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=445, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=490, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=540, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=595, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=655, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=721, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=794, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=874, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=962, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=1059, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=1165, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=1282, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=1411, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=1553, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=1709, ac_busy_delay=0
Started by GNU MCU Eclipse
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : accepting ‘gdb’ connection on tcp/3333
openocd: src/target/riscv/riscv-013.c:993: register_read_direct: Assertion `number != GDB_REGNO_S0’ failed.

How to solve this problem?

2

What platform are you on? (Windows, MacOS X or Linux)

and What hardware are you connecting to? (HiFive1, ARTY/E31, ARTY/E51 or HiFive Unleashed)

and Did you get OpenOCD from the OpenOCD site or from the SiFive Repo at https://github.com/riscv/riscv-openocd ? (I think we’re still trying to upstream all the changes in the SiFive repo to the official OpenOCD repo.)

and which CFG file are you using?

-Cheers
-M

3

Thanks for your reply!
I use Linux.

My hardware use Nexys4 DDR, and I use repo https://github.com/sifive/freedom and fix some fpga configuration files, then generate bit file.
I want to implement on Nexys4 DDR, Arty and Nexys4 DDR both use the xc7a100tcsg.

I get OpenOCD from the SiFive Repo.

I use cfg file which is the same as the Arty cfg.

4

There are several Arty config files. Can you just include your cfg file contents here?

5

Of course, this is my cfg file:

adapter_khz 10000

#source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]

interface ftdi
ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
ftdi_vid_pid 0x15ba 0x002a

ftdi_layout_init 0x0808 0x0a1b
ftdi_layout_signal nSRST -oe 0x0200
ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
ftdi_layout_signal LED -data 0x0800

set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1

flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME 0x10014000
init
#reset
if {[ info exists pulse_srst]} {
ftdi_set_signal nSRST 0
ftdi_set_signal nSRST z
}
halt
#flash protect 0 64 last off

6

Would you please share your modifications through porting freedom to nexys 4 ddr? Im doing the same but still cannot connect to CPU through JTAG. Since I dont have an golden reference I cannnot find out the reason.