FE310 Documentation issues?

Hi, I’m currently reading the docs for the FE310, and in section 8.3.2 the following statement is made about vectored mode:

“In vectored interrupt mode, BASE must be 64-byte aligned”.

Now, this seems a bit weird. The privileged specs mentions “The value in the BASE field must always be aligned on a 4-byte boundary”. The thing is: the same statement about 64-byte alignment is made multiple times throughout the section, which only serves to increase my confusion.

The priv spec says “The value in the BASE field must always be aligned on a 4-byte boundary, and the MODE setting may impose additional alignment constraints on the value in the BASE field.” Two paragraphs down it says “An implementation may have different alignment constraints for different modes. In particular, MODE=Vectored may have stricter alignment constraints than MODE=Direct.” Then there is a footnote that says “Allowing coarser alignments in Vectored mode enables vectoring to be implemented without a hardware adder circuit.” It looks like the wording changes a bit from version to version, I’m looking at the current draft.

There are less than 16 exception codes, and 16*4 is 64. So with 64-byte alignment for the base in vectored mode, we take the high bits from base and the low bits from the exception and there is no adder required.

I see, thank you for the explanation!