Synchronous Interrupts


#1

Please, could you help me with a question on interrupts?
I’m exploring the E31 features by reading through the document SiFive E31 Core Complex Manual v2p0.
There are two modes of operation.
Direct Mode: All exceptions set pc to mtvec.BASE
Vectored Mode: Asynchronous interrupts set pc to mtvec.BASE + 4 × exception code.
So what happens to synchronous interrupts in Vectored Mode? Are they lost in space? =)
Thank you!


(Krste Asanovic) #2

From RISC-V Privileged Architecture Specification:
“When MODE=Vectored, all synchronous exceptions into machine mode cause the pc to be set to the address in the BASE field, whereas interrupts cause the pc to be set to the address in the BASE field plus four times the interrupt cause number.”


#3

I’ve just tested it and it worked fine. Thank you very much!