Correct PLIC claim/complete register addresses


Are the addresses for the PLIC claim/complete registers given in the SiFive FU740-C000 Manual (chapter 13) correct?

For example the claim/complete register for Hart 0 M-Mode offset is 0x20_0008 according to the manual.

But according to the RISC-V PLIC Specification the offset for context 0 should be 0x20_0004.

What am I missing?

Good catch, @simon either Table 58 has a typo for addresses of Claim/Complete and the Interrupt Enables for all of the Harts (0x…08 should be 0x…04, as the Table’s header alludes, “Only naturally aligned 32-bit memory accesses are required.”);
or, indeed being a 64-bit architecture, everything is laid out on an 8-Byte (not a 4-Byte) boundary where 0x…08 is correct for Claim/Complete.

Suggest making a quick stand-alone test or gdb session to probe and check.

1 Like

Table 58 is wrong. The memory-mapped registers are 4 bytes in size and alignment.


Thanks for your answers,

When using the 0x…04 offsets, everything works fine.

1 Like