Hi,
Point 1 - The Interrupt is not working
Point 2 - The Interrupt is working
The SiFive PLIC is tested on the Microchip PolarFire SoC.
1). The Interrupt does not occur when disabling the interrupt before interrupt complete, Is this expected behaviour with the SiFive PLIC?
With below Pseudo code, Claim the interrupt number and a call to the handler, the interrupt is disabled in the handler and there is no impact on the Interrupt Complete register when writing with the interrupt number, so the next interrupt(same) doesn’t occur even though the interrupt is enabled.
PLIC External Interrupt ISR Pseudo Code**********
void handle_m_ext_interrupt(void)
{
int_num = PLIC_ClaimIRQ(); /* get interrupt number by reading interrupt claim register /
ext_irq_handler(int_num); / service the interrupt handler /
PLIC_CompleteIRQ(int_num); / Clear interrupt claim/complete register /
PLIC_EnableIRQ(int_num); / enable interrupt here or later /
}
void ext_irq_handler(int_num)
{
PLIC_DisableIRQ(int_num); / disable interrupt */
}
2). The Interrupt occurs when the interrupt complete is cleared before disable the interrupt and getting the next interrupt.
PLIC External Interrupt ISR Pseudo Code**********
void handle_m_ext_interrupt(void)
{
int_num = PLIC_ClaimIRQ(); /* get interrupt number by reading interrupt claim register /
ext_irq_handler(int_num); / service the interrupt service handler /
PLIC_EnableIRQ(int_num); / enable interrupt here or later /
}
void ext_irq_handler(int_num)
{
PLIC_CompleteIRQ(int_num); / Clear interrupt claim/complete register /
PLIC_DisableIRQ(int_num); / disable interrupt */
}
Regards
Padmarao