Has any successfully used the Xilinx BSCAN primitive to debug a RISCV core sitting on an FPGA? If so, what software modifications (if any) were necessary to use OpenOCD or other JTAG debugging software (i.e. Xilinx XSDB)?
The microblaze core uses the BSCAN primitive for debugging, so I would like to do something similar with a RISCV core. However, BSCAN requires the use of the USERX command, so I don’t think it is quite as straight forward as creating a openocd configuration similar to those in riscv-tests/debug.
Thanks for sharing! - I’ll follow up if I find a solution.