What's the point about UART1?

Hi everyone,

I was wondering why there is a UART1 interface inside the FE310-G000 Chip. According to the BSP the GPIO pins for the UART core are GPIO 24 and 25. However the pinout of the chip only goes up to GPIO pin 23.
My question is now: Is there some trick to enable the second UART or is it not at all usable on the FE310-G000 chip?

Thanks in advance, Ben

“Table 1.1: FE310-G000 Feature Summary Table. Note that the FE310-G000 contains features in silicon which are available to software, but are not connected to pads on the [QFN48] package.”

UART0 is connected to pins. UART1 is not. QSPI2 is not connected to pins. QSPI1 has only three of four chip select signals connected to pins.

Presumably QFN48 was the cheapest or most convenient package for the initial production run, even though it doesn’t have enough pins for all features present in silicon to be exposed. The same FE310-G000 die could in future be made available in a different physical package with more or differently-connected pins for basically zero engineering cost.

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Correct- not all chip pads are bonded out. We chose QFN48 as tradeoff between pin count and package size/cost. Engineering cost is not huge, but non-zero, to support different package sizes in production.

Is it planned to produce chips with larger pin count to enable the use of all components of the chip?

We are working on more production parts with different sets of features, to be announced in due course.