What is the use of mip csr while mcause gives complete picture?

HiFive1 Rev B
1

I understood that mcause csr should give complete picture of which interrupt pending and reason for the same. In this context is the mip register redundant? How to use both if necessary? Here is my timer interrupt handler example.

	// Read mcause register to know reason for interrupt
asm volatile ("csrr %0, mcause" : "=r"(mcause));
if (0x80000007 == mcause) {

	// TODO: mip.mtip is redundant here?