I use HiFive1 Rev-B board. I refer FE310-G002 manual for interrupt handling. I don’t understand how to clear an interrupt in interrupt handler so that handler won’t be called infinitely.
For example for timer interrupt, I just disable the timer interrupt (clear mie.mtie) itself in handler. For Software interrupt, I just set 0x0 on MSIP register in CLINT memory map. Not sure is this the right way to do it?
It depends on the interrupt type how to clear it.
In general the m-mode pending bits in mip csr are read-only and just reflect the status of the interrupt source.
The timer interrupt for example is cleared with writing a new value to the mtimecmp register (which must be higher than the current timer value).
Imagine mip.mtip just as the output of the timer comparator.
An external interrupt must be cleared in the external interrupt controller, which is often a RISC-V PLIC.
BTW: You should read the RISC-V privilege architecture spec in addition to the FE310 manual. The SiFive doc assumes that the reader is familiar with the RISC-V specifications.
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Thanks, it is helpful. Yes, I have started going through RISC-V specifications.