To get the base width of CPU capability from MISA register, what is the best way to read MISA register?
As per privileged spec, MISA CSR length should be base width wide. Also, its MXL field holds the MXLEN.
Now, ignoring 128 bits, if I assign MISA address to long long pointer (pointer to 64 bits) and read it as 64bits (assuming it is) and if the MISA CSR actually is just 32 bits wide will it create a fault?
Would be great to know how do you read the MISA register without knowing its width?
MISA is a CSR i.e. a special register, not a memory location. As with any register, you can not access it using a C pointer. You can only use a CSR machine code instruction.
so, CSRs are not memory mapped.
Then should CSR read/write functions should be only in RISC-V assembly and C can just invoke those assembly functions; is this the only way?
Could you point out any reference doc/implementation?
From the RISC-V Privileged Specs doc
The base width can also be found if misa is zero, by placing the immediate 4 in a register then shifting the register left by 31 bits at a time. If zero after one shift, then the machine is RV32. If zero after two shifts, then the machine is RV64, else RV128
You can read misa with an extended asm. See for instance
https://github.com/sifive/example-user-mode/blob/master/example-user-mode.c#L35
though the use of int looks wrong for a 64-bit system. Should be a type with the same width as XLEN. Though this is just a testcase to generate an illegal instruction trap in user mode so it doesn’t matter. This is a submodule of freedom-e-sdk. You can find a lot of code samples in freedom-e-sdk/software.
I updated my Rust program that reads the MISA register of the HiFive1 Rev B, and I was verifying the contents were correct. The extensions match dead on, but the MXL didn’t. according the the privileged architecture doc, the two most sig digs of the register is the base ISA width. The table says 11 is 128, 10 is 64 and 01 is 32 bit. I’m getting back that the HiFive is 10 which is 64 bit?? Am I missing something here?
EDIT Notice in my extensions print I have UV, but should be VU
You only printed 31 bits. If you print all 32 bits then you should get 01 as the top two bits.
Wow, I can’t believe I missed that. I counted it twice and was thinking it was all 32 bits confusing indexing starting with 0 so 32nd bit is 31. It was actually only 31 total bits haha. Thanks!
Is there any defined calling convention for RUST on risc-v ?
When I tried to do the same thing, could n’t find calling convention for rust. I want the parsing in rust & reading misa in assembly and pass back to rust function. Could you share the calling convention for rust on risc-v?
Rust has FFI that provides interoperability between Rust and C/assembly code. You can declare your misa read function as extern "C" and call it from Rust as any other function. In fact, there is already a wrapper in the riscv crate for this: just call riscv::register::misa::read() and get the result.