What is Chiplink Domain #1-7 Prefetch?


(Farzad Farshchi) #1

In the list of L2 masters what is Chiplink Domain #1-7 Prefetch? I understand what Chiplink domain means. My question is about the meaning of “Prefetch”.


(Wesley W. Terpstra) #2

ChipLink order domains must execute their reads/writes in FIFO order. However, there is a component in the SoC which snoops ahead of the currently active reads/writes to find stuff that will come later and it prefetches that data.


(Farzad Farshchi) #3

Which component are you referring to? Is this related to TileLink Hint operations?


(Farzad Farshchi) #4

I’m asking this because I see an impact on NVDLA performance when I set the way mask to 0x0 for this domain. So, there must be accesses in prefetch domain by NVDLA (alongside the accesses on non-prefetch domains). I’d like to know how some of the accesses by NVDLA are directed to prefetch domain.


(Wesley W. Terpstra) #5

All accesses that come in via ChipLink but which are stalled due to AXI ordering requirements will generate prefetches/Hints from the prefetch master you are asking about.