I porting over academic research from RISC application specific integrated processors (ASIP) using static/reconfigurable instruction set (ISA) extensions. The provided documentation is vague on the process for integrating IP into the pipeline through ISA extensions with the tools extension.
IP is generated from pipe-lined ROCCC and customized numeric systems blocks. The intended usage is for machine learning and artificial intelligence research. All of the IP is generated in VHDL is planned to used TCM for data staging.
Question: Where can I find the detailed information to integrate within the system hardware and tool chain environment for custom IP ISA extensions?
ROCCC Data Path Compiler
Thanks in Advance,