Looks good @SJain you might like the interrupt procedural flow illustration and somewhat related discussion.
It’s not clear to me how synchronous interrupts, those with a positive mcause value such as the exceptions, are handled in Vectored mode. Could it be that, in Vectored mode, you always see BASE+0 because you’re getting an Instruction address misaligned exception – which happens to be mcause=0, without the msb?
You can see a fairly complete MTVEC Demonstration in the start.s file.
As @RalphF mentions, you want to make sure that your vectored handler (the trap_handler in line 77 of the Demonstration) is on an 4-byte boundary for Direct operation, and 64-byte boundary for Vectored operation. See Assembler Directives for description of the GNU Assembler.
Vectored mode lets you bypass the testing and arithmetic of mcause, but in the case of an external interrupt you still need to do the testing and arithmetic of the PLIC Claim procedure (i.e., int_external_m_mode in the Demonstration).