Trap handling support for user mode


Is trap handling in user mode supported in Hifive1 Rev B ? I don’t find utvec register in FE310 manual.

If user trap handling is NOT supported (& there is NO supervisor mode), is it right to assume, with privilege state in user mode if trap occurs, the execution would jump into the address mapped to mtvec register?

That would be a good assumption @bsvtgc
As Bruce mentions, the FE310-G002 SoC does indeed have User Mode, as noted in the FE310-G002 Manual (v19p04):

The E31 supports RISC‐V user mode, providing two levels of privilege: machine (M) and user (U). U-mode provides a mechanism to isolate application processes from each other and from trusted code running in M-mode.

An earlier draft of the Privileged Spec (v1.10) shows the User-level ustatus, uie, and utvec CSR’s in Table 2.2 on page 9. These have since been removed in the latest Privileged Spec (v1.12, 2021-12-03), where User-mode has been renamed to “unprivileged”; see Table 2.2 on page 8.

Section 1.6 (Exceptions, Traps, and Interrupts) of the Unprivileged Spec, especially Table 1.1, gives some description of trap handling in U-mode.