farzad
January 15, 2019, 2:09am
1
I got this error while integrating NVDLA into Rocket Chip from Sept 25th:
[error] java.lang.IllegalArgumentException: requirement failed: There is no TLError reachable from AXI4ToTL. One must be instantiated.
Does anyone know what is happening here and how this should be fixed?
Thanks,
henry
January 15, 2019, 2:28am
2
The AXI4ToTL converter depends on having a downstream error device available to bounce non-compliant traffic while preserving AXI ordering semantics without requiring the adapter to have internal state.
The default RocketChip configuration provides such a device here:
case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
case XLen => 64 // Applies to all cores
case MaxHartIdBits => log2Up(site(RocketTilesKey).size)
// Interconnect parameters
case SystemBusKey => SystemBusParams(
beatBytes = site(XLen)/8,
blockBytes = site(CacheBlockBytes))
case ControlBusKey => PeripheryBusParams(
beatBytes = site(XLen)/8,
blockBytes = site(CacheBlockBytes),
errorDevice = Some(DevNullParams(List(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=4096)),
replicatorMask = site(MultiChipMaskKey))
case PeripheryBusKey => PeripheryBusParams(
beatBytes = site(XLen)/8,
blockBytes = site(CacheBlockBytes))
case MemoryBusKey => MemoryBusParams(
beatBytes = site(XLen)/8,
blockBytes = site(CacheBlockBytes),
replicatorMask = site(MultiChipMaskKey))
case FrontBusKey => FrontBusParams(
beatBytes = site(XLen)/8,
But perhaps you have modified the bus architecture significantly? You can add one to any CanHaveBuiltInDevices child class (e.g. any of the TLBusWrappers) using the same argument to the HasBuiltInDeviceParams child case class. You could also add one by hand using this as an example:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
trait HasBuiltInDeviceParams {
val zeroDevice: Option[AddressSet]
val errorDevice: Option[DevNullParams]
}
/* Optionally add some built-in devices to a bus wrapper */
trait CanHaveBuiltInDevices { this: TLBusWrapper =>
def attachBuiltInDevices(params: HasBuiltInDeviceParams) {
params.errorDevice.foreach { dnp => LazyScope("wrapped_error_device") {
val error = LazyModule(new TLError(
params = dnp,
show original
farzad
January 15, 2019, 6:38pm
3
Thanks a lot for this! Since I was using an older version of Rocket Chip, I had to copy and paste the line below to add the error device.
/** Example Top with periphery devices and ports, and a Rocket subsystem */
class ExampleRocketSystem(implicit p: Parameters) extends RocketSubsystem
with HasAsyncExtInterrupts
with CanHaveMasterAXI4MemPort
with CanHaveMasterAXI4MMIOPort
with CanHaveSlaveAXI4Port
with HasPeripheryBootROM {
override lazy val module = new ExampleRocketSystemModuleImp(this)
// Error device used for testing and to NACK invalid front port transactions
val error = LazyModule(new TLError(p(ErrorDeviceKey), sbus.beatBytes))
// always buffer the error device because no one cares about its latency
sbus.coupleTo("slave_named_error"){ error.node := TLBuffer() := _ }
}
class ExampleRocketSystemModuleImp[+L <: ExampleRocketSystem](_outer: L) extends RocketSubsystemModuleImp(_outer)
with HasRTCModuleImp
with HasExtInterruptsModuleImp
with CanHaveMasterAXI4MemPortModuleImp
with CanHaveMasterAXI4MMIOPortModuleImp
with CanHaveSlaveAXI4PortModuleImp