Stuck at "Starting target CPU.." with J-Link EDU downloading Blinky to FE310 FPGA coreplexIP


#1

Hello,

I’m trying to test the FE310 softcore on Arty Artix-7 35T board with some programs. I don’t have a Olimex-ARM-USB-H but I do have a J-Link EDU, which, according SEGGAR, supports the RISC-V FE310 coreplexIP. I followed carefully the instructions from “SiFive-E310-arty-gettingstarted-v1.0.6.pdf” and downloaded the “sifive_coreip_E31_FPGA_Evaluation_v3p0_0.mcs” bitstream to the board with Vivado Hardware Manager. The default program coupled with the mcs runs successfully with one tri-color LED flashing and the SiFive logo appears on PC serial terminal.

Then I followed the instructions from
https://wiki.segger.com/SiFive_Arty_FPGA_Dev_Kit
and used Freedom Studio to debug the app “Blue Blinky”, and this is when the problem came up. The following is the log info:

SEGGER J-Link GDB Server V6.33g (beta) Command Line Version

JLinkARM.dll V6.33g (DLL compiled Jun 28 2018 15:09:48)

Command line: -if jtag -device RISC-V -endian little -speed 4000 -port 2331 -swoport 2332 -telnetport 2333 -vd -ir -localhostonly 1 -singlerun -strict -timeout 0 -nogui
-----GDB Server start settings-----
GDBInit file: none
GDB Server Listening port: 2331
SWO raw output listening port: 2332
Terminal I/O port: 2333
Accept remote connection: localhost only
Generate logfile: off
Verify download: on
Init regs on start: on
Silent mode: off
Single run mode: on
Target connection timeout: 0 ms
------J-Link related settings------
J-Link Host interface: USB
J-Link script: none
J-Link settings file: none
------Target related settings------
Target device: RISC-V
Target interface: JTAG
Target interface speed: 4000kHz
Target endian: little

Connecting to J-Link…
J-Link is connected.
Firmware: J-Link V10 compiled Jun 27 2018 10:57:29
Hardware: V10.10
S/N: 260109090
OEM: SEGGER-EDU
Feature(s): FlashBP, GDB
Checking target voltage…
Target voltage: 3.27 V
Listening on TCP/IP port 2331
Connecting to target…
J-Link found 1 JTAG device, Total IRLen = 5
JTAG ID: 0x20000001 (RISC-V)
Connected to target
Waiting for GDB connection…Connected to 127.0.0.1
Reading all registers
Reading register (PC = 0x00000000)
Received monitor command: speed 4000
Target interface speed set to 4000 kHz
Received monitor command: clrbp
Received monitor command: reset
Resetting target
Received monitor command: halt
Halting target CPU…
…Target halted (PC = 0x404002CA)
Received monitor command: regs
X0 = 00000000, X1 = 4040010A, X2 = 8000FFE0, X3 = 800007C0
X4 = 00000000, X5 = 00000000, X6 = 00000010, X7 = 404007C0
X8 = 01484812, X9 = 00000000, X10= 01484817, X11= 00000000
X12= 014849A2, X13= 00000000, X14= 000000FF, X15= 00000000
X16= 0200C000, X17= 00000000, X18= 02000080, X19= 00000000
X20= 00000000, X21= 00000000, X22= 00000000, X23= 00000000
X24= 00000000, X25= 00000000, X26= 00000000, X27= 00000000
X28= 20005000, X29= 0000002F, X30= 000000FF, X31= 00000000
PC = 404002CA
Reading register (PC = 0x404002CA)
Received monitor command: speed 4000
Target interface speed set to 4000 kHz
Received monitor command: flash breakpoints 1
Flash breakpoints enabled
Reading all registers
Downloading 108 bytes @ address 0x40400000 - Verify failed
Downloading 2534 bytes @ address 0x4040006C - Verify failed
Downloading 59 bytes @ address 0x40400A54 - Verify failed
Downloading 44 bytes @ address 0x40400A90 - Verify failed
Downloading 1072 bytes @ address 0x40400ABC - Verify failed
Writing register (PC = 0x40400000)
Reading register (MISA = 0x40101105)
Read 2 bytes @ address 0x40400552 (Data = 0x2020)
Received monitor command: clrbp
Received monitor command: reset
Resetting target
Received monitor command: halt
Halting target CPU…
…Target halted (PC = 0x404002CA)
Reading register (PC = 0x404002CA)
Reading all registers
Reading 64 bytes @ address 0x01484800
WARNING: Failed to read memory @ address 0x01484800
Read 4 bytes @ address 0x0148480E (Data = 0x24232423)
Reading 64 bytes @ address 0x01484800
WARNING: Failed to read memory @ address 0x01484800
Read 4 bytes @ address 0x0148480E (Data = 0x24232423)
Reading 64 bytes @ address 0x01484800
WARNING: Failed to read memory @ address 0x01484800
Read 4 bytes @ address 0x0148480E (Data = 0x24232423)
Reading 64 bytes @ address 0x01484800
WARNING: Failed to read memory @ address 0x01484800
Read 4 bytes @ address 0x0148480E (Data = 0x24232423)
Reading 64 bytes @ address 0x01484800
WARNING: Failed to read memory @ address 0x01484800
Read 4 bytes @ address 0x0148480E (Data = 0x24232423)
Read 2 bytes @ address 0x40400552 (Data = 0x2020)
Received monitor command: regs
X0 = 00000000, X1 = 4040010A, X2 = 8000FFE0, X3 = 800007C0
X4 = 00000000, X5 = 00000000, X6 = 00000010, X7 = 404007C0
X8 = 01484812, X9 = 00000000, X10= 01484817, X11= 00000000
X12= 014849A2, X13= 00000000, X14= 000000FF, X15= 00000000
X16= 0200C000, X17= 00000000, X18= 02000080, X19= 00000000
X20= 00000000, X21= 00000000, X22= 00000000, X23= 00000000
X24= 00000000, X25= 00000000, X26= 00000000, X27= 00000000
X28= 20005000, X29= 0000002F, X30= 000000FF, X31= 00000000
PC = 404002CA
Reading register (PC = 0x404002CA)
Setting breakpoint @ address 0x40400552, Size = 2, BPHandle = 0x0001
Starting target CPU…

And it just stuck at Starting target CPU… and apparently the Blue Blinky was not flashed to QSPI Flash as I pushed the reset button.

This is quite annoying and can some one please help? (I also tried to run other apps like the dhrystone and coremark example ones but all ended up stuck at Starting target CPU…

Thanks


(Tommy Murphy) #2

Seems to me like you first need to figure out why all the verify operations after download are failing?


#3

The project “Blue Blinky” I ran on Freedom Studio was downloaded from
https://wiki.segger.com/SiFive_Arty_FPGA_Dev_Kit
and the C source code for that program is here:

#include <stdint.h>
#include <stdbool.h>
#include <stdatomic.h>
#include “encoding.h”
#include <platform.h>

#ifndef _SIFIVE_COREPLEXIP_ARTY_H
#error ‘coreplexip_welcome’ demo only supported for Coreplex IP Eval Kits
#endif

static void _Delay(volatile unsigned int DelayLoops) {
while(–DelayLoops);
}

int main (void){
unsigned char LEDState;
volatile int i;
//
// Set up RGB PWM
//
PWM0_REG(PWM_CFG) = 0;
PWM0_REG(PWM_CFG) = (PWM_CFG_ENALWAYS) | (PWM_CFG_ZEROCMP) | (PWM_CFG_DEGLITCH);
PWM0_REG(PWM_COUNT) = 0;
PWM0_REG(PWM_CMP0) = 0x88; // Half power for the RGB LED
PWM0_REG(PWM_CMP1) = 0xFF; // Red LED == off
PWM0_REG(PWM_CMP2) = 0xFF; // Green LED == off
PWM0_REG(PWM_CMP3) = 0xFF; // Blue LED == off
do {
PWM0_REG(PWM_CMP3) = 0x44; // Blue LED == on
_Delay(10000000);
PWM0_REG(PWM_CMP3) = 0xFF; // Blue LED == off
_Delay(10000000);
} while (1);
}

However, the project still contains a .cfg file which uses Olimex-ARM-USB-H as debugger:

JTAG adapter setup

adapter_khz 10000

interface ftdi
ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
ftdi_vid_pid 0x15ba 0x002a

ftdi_layout_init 0x0808 0x0a1b
ftdi_layout_signal nSRST -oe 0x0200
#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
ftdi_layout_signal LED -data 0x0800

set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001

set _TARGETNAME $_CHIPNAME.cpu

target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1

Un-comment these two flash lines if you have a SPI flash and want to write

it.

flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
init
if {[ info exists pulse_srst]} {
ftdi_set_signal nSRST 0
ftdi_set_signal nSRST z
}
halt
flash protect 0 64 last off
echo “Ready for Remote Connections”

I’m not sure if the problem occurred as a result of incompatibility of the J-Link debugger and the cfg file?

Other than that, I carefully checked all the hardware connections between J-Link and Arty Pmod JD as well as GDB Server / Client settings of Freedom Studio and they all seem ok.

For GDB client, the riscv-none-embed-gdb is used.