SPI CS pin rises too early

@Gaz, I apologize for the long delay. The two undocumented fields relating to SPI operation are ‘extradel’ and ‘sampledel’. They may be able to help solve the issue you observe.

The SPI blocks at 0x10014000 , 0x10024000 , and 0x10034000 have two very important registers not shown in Chapter 19, Table 65 of the Manual:
extradel : 0x38
sampledel : 0x3c

You can see how these are implemented at the two git links here:
Implementation of sampledel and extradel adjustments to SPI
asic circuit code

Also, you probably are already aware of the missing descriptions for rhe GPIO settings for IOF control, defined in the src/drivers/sifive,gpio0.c file
#define GPIO_IOF_EN (0x38)
#define GPIO_IOF_SEL (0x3C)

The suggestion of @CoolJuniper to use CSMODE (and its conjugate pair to release the CS) is also an excellent idea.

These are three other useful discussions on the subject:
Freedom Metal Register Addresses Header File
FE310-G000 manual is missing the GPIO IOF mappings
SiFive FE310-G002 Manual v19p05 missing GPIO IOF mapping