I’m using the hifive1 for a little personal project, connecting it to an ADC (MCP3202) via SPI1. I have a couple questions about interfacing with the ADC.
Regarding IOF, does enabling the IOF let the hardware control the configuration of the hardware pins so “manual” GPIO configuration is not required, similar to the UART?
Can the FE310-G receive a message from the ADC when it expects us to write three bits and receive 13? If so, what is the best way to accomplish this with the SPI1?
regarding IOF, does enabling the IOF let the hardware control the configuration of the hardware pins so “manual” GPIO configuration is not required, similar to the UART?
Yes, exactly like the UART. You enable the IOF for each individual pin using IOF_EN. For the SPI peripheral you will want the corresponding IOF_SEL bits set to 0.
2) Can the FE310-G receive a message from the ADC when it expects us to write three bits and receive 13? If so, what is the best way to accomplish this with the SPI1?
If I am properly understanding your question, I believe you can ensure the SPI is configured for RX, then write to TX the 3 bits you care about followed by 13 “dummy” bits. Then you should be able to read 3 “dummy” bits as well as 13 real bits from the RXDATA register. Of course you will need to divide this into two byte-wise operations, but since the TX and RX FIFOs can hold more than 1 entry, you can still do all the TX_DATA writes followed by the RX_DATA reads.
But wouldn’t CS count each octet as a frame? That would interrupt the TX from the slave and drop the lower 8 bytes. In the FMT register, it looks like a maximum frame size is 8 bits, so wouldn’t it count each write to TXDATA as a frame?
I was hoping to not have to test this manually to see if it works. Trying to optimize my time
