Simulating DebugModule in E31 with verilator

Hi all,

I have been trying to evaluate the E31 RTL by simulating via verilator. The initial test-bench works well, and I can run programs. However, I am unable to access the Debug Module via DebugDriver and DebugTests as documented in User Guide (Section 7.9). I have instantiated DebugDriver and DebugTests in

DebugDriver DebugDriver(

  DebugTests #(.verbose(2), .ram_address(64'h80000000)) DebugTests ();

And initialized the tests in the initial block of the CoreIPSubsystemAllPortRAMTestHarness.


However, when I run the simulation, it gives the following error.

**FAILURE** WaitDMI 10 00000001 timeout
- rtl/testbench/DebugDriver.v:226: Verilog $finish
**FAILURE** dmcontrol read after ActivateDM:
00000001 = Expected
00000000 = Actual
- rtl/testbench/DebugTests.v:378: Verilog $finish

Any ideas what is wrong ?