Simulating DebugModule in E31 with verilator

HiFive1 Rev B
1

Hi all,

I have been trying to evaluate the E31 RTL by simulating via verilator. The initial test-bench works well, and I can run programs. However, I am unable to access the Debug Module via DebugDriver and DebugTests as documented in User Guide (Section 7.9). I have instantiated DebugDriver and DebugTests in CoreIPSubsystemAllPortRAMTestHarness.sv.

...
DebugDriver DebugDriver(
    .debug_systemjtag_reset(system_debug_systemjtag_reset),   
    .debug_systemjtag_jtag_TCK(system_debug_systemjtag_jtag_TCK),
    .debug_systemjtag_jtag_TMS(system_debug_systemjtag_jtag_TMS),
    .debug_systemjtag_jtag_TDI(system_debug_systemjtag_jtag_TDI),
    .debug_systemjtag_jtag_TDO_data(system_debug_systemjtag_jtag_TDO_data),
    .debug_systemjtag_jtag_TDO_driven(system_debug_systemjtag_jtag_TDO_driven)
  );

  DebugTests #(.verbose(2), .ram_address(64'h80000000)) DebugTests ();
...

And initialized the tests in the initial block of the CoreIPSubsystemAllPortRAMTestHarness.

DebugTests.RunTests;

However, when I run the simulation, it gives the following error.

**FAILURE** WaitDMI 10 00000001 timeout
- rtl/testbench/DebugDriver.v:226: Verilog $finish
**FAILURE** dmcontrol read after ActivateDM:
00000001 = Expected
00000000 = Actual
- rtl/testbench/DebugTests.v:378: Verilog $finish

Any ideas what is wrong ?

2

Hi utsav dayal,

please check table.28 in user_guide.pdf.
and please check requirement of JTAG frequency.

and I’m stuck to ‘Halting hart 0’
if you figure out solution, please share.

thanks