Hi, I am using an Arty7 (incorporating the FPGA Xilinx Artix A100T), as suggested in the official document “SiFive Core IP Arty FPGA Eval Kit User Guide”, to test the E24 core (beacuse my company is evaluating to buy its license). I am following the steps described in the document above-mentioned, then I program the FPGA with the provided bitstream (arty_a7_100t-sifive/design-arty) and I am running on the SoC E24-based some simple benchmarks starting from the provided examples. I come across a strange outcome as regards the core clock frequency. In accordance with my computation and measurements, the resulting clock frequency is about 32 kHz; on the other hand it is written still in the above-mentioned guide that the provided SoC image for the Arty7 uses clocks running at 32.5 MHz.
Then, my question is… is there anything which can limit the actual core clock frequency in the provided bistream (dev kit E24 for Arty7) ? Is there a way to verify which is the current actual clock frequency running on the SoC? I hoped that in the pinout there was a clock copy dumped out as output, but I saw there is not. I even tried to use the function “metal_clock_get_rate_hz” with no success.
Thanks,
EAG