The Arty boasts internal clock speeds of +450MHz as well as running the Xilinx Microblaze at +200MHz. Is there a reason why the freedom-e-sdk/bsp/env/freedom-e300-arty/init.c is hard coded at 65MHz? Can I safely change that value in the init.c or must I consider other coding as well?
In FPGAs, the complexity of the design determines the maximum device speed. If the timing checks pass, the FPGA vendors/tools guarantee that the design will run at that speed (and below) on that grade of FPGA.
So it all depends on what timing constraints have been applied when the design was implemented. If you are building the design yourself then you can change the constraints and see if it is workable.
Thanks Mike, I appreciate your insight. I understand that, but I am referring to the SiFive FPGA design for the Arty. I want to know whether or not the 65MHz was chosen due to limitations SiFive had encountered in their design, and if it is “safe” to change in regard to other possible dependancies, e.g. UART communication etc.
Oh, I see what you mean! Yeah, software support is a different kettle of fish that what clock frequency the FPGA design might support, but the FPGA design’s Fmax will set the upper limit of the “guaranteed to work over all temperature ranges and on every board” range.
If I had to make a very uninformed guess, I suspect the clock settings must match the PLL parameters used for the HDL design’s PLL settings…
Well, after skimming through the HDL code it appears that the 65MHz is hard coded, so the init.c parameter seems to be there just for information purposes and not an actual clock set parameter, making my 2nd question senseless.