RISC-V floating point registers

In RISC-V spec version 2.2 it defines 32 Floating point registers (both SP and DP registers are same) When doing SP operation, the result is 32-bit but this value we need to store in a 64-bit resisters.

My question is whether this 32-bit data (single precision) will be sign extended or zero extended to make 64-bit ?

Sign and zero extension are concepts that only apply to integers. You can’t do that to FP values.

The ISA manual, in section 9.2, says that 32-bit FP values in 64-bit registers are NaN-boxed, so that if you read a 64-bit value you get a NaN. See the ISA manual for more info.

When SP values are stored in DP registers, the upper bits are filled
with ones (irrespective of the sign of the SP value). This scheme is
described in Sec. 9.2, “NaN Boxing of Narrower Values.”