RISCV Floating Point


(Karthik) #1

Hi,

I have implemented RISC-V rv32im core and planning to add floating-point support. I want to consider only the below instructions for hardware implementation and for the rest of the instructions in floating-point, I want the compiler to take care. How to modify the compiler to include the above functionality?

flw
fsw
fadd.s
fsub.s
fmul.s
fmv.s.w
fmv.w.s
fsgnj.s
fsgnjn.s
fsgnjx.s
feq.s
flt.s
fle.s
fmin
fmax
fcvt.x.w
fcvt.x.wu
fcvt.w.x
fcvt.wu.x

Thanks
Karthik


(Bruce Hoult) #2

Hi Karthik,

I think you’d find a lot more advice about this question on a general RISC-V forum such as the sw-dev mailing list, rather than on this forum which is for SiFive products.

It would be more normal (although lower performance) to allow the unimplemented instructions to trap and then emulate them.

The compiler of course already knows how to emulate the missing operations using integer instructions, as you’ll already see when you compile for RV32IM. So if you want to modify the compiler the main thing you’d need is to make a selected combination of the soft float and hard float code generation, but you’d also have to copy the value from FP registers to integer registers.

It may also be higher performance to use the FP instructions you do have to help emulate the missing ones. In that case you’d be up for custom FP library development too.


(Jim Wilson) #3

If you specify an arch that contains f but not d, then gcc will emit the f instructions but not the d instructions. That is mostly what you want.

If you want something more refined than that, then you need to add a new flag to gcc to specify the instructions you want. We currently have TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT which map to f and d. The flags are defined in gcc/config/riscv/riscv.opt, e.g. Mask(HARD_FLOAT). They are set in gcc/common/config/riscv/riscv-common.c. They are tested in gcc/config/riscv/riscv.md which contains the machine description patterns for each instruction. Find each FP instruction and make sure it is enabled/disabled depending on your new flag. You might also have to modify some code in riscv.c, as some instructions are emitted by functions in that file.


(Bruce Hoult) #4

I was working from the basis that there are a number of single precision operations missing in the list. I took RV32IMF as read as the base point.

The most obvious are divide, square root, classify (a cheap operation! Why leave it out?), and the entire FMA family. I didn’t check if there is anything else.