PLIC interfaced to Multiple CPUs

As per PLIC description it can support 1023 interrupt sources targeting up to 15,872 hart contexts.
If priorities are not assigned then lowest id will have highest priority.

Suppose Interrupt ID 10 assigned to CPU1 and Interrupt ID 20 assigned to CPU2

Interrupt ID 10 -------> CPU1
Interrupt ID 20 -------> CPU2

If both interrupts arrived at same time, then how PLIC will handle it?

My understanding it

  1. PLIC will raise int (for ID10) CPU1
  2. CPU1 will service the interrupt and complete it.
  3. PLIC will raise int (for ID20) to CPU2
  4. CPU2 will service the interrupt and complete it.

If my understanding is correct then if CPU1 hung in to ISR due to some reasons and interrupt request didn’t get serviced then whole system will hang.


I am going to assume that “Interrupt ID 10 assigned to CPU1” means that only CPU1 has this interrupt 10 enabled, i.e. CPU2 has interrupt 10 disabled. In that case, both CPUs will be interrupted simultaneously, and when they read their claim registers, they will be told to service interrupt 10 and 20 respectively. When they are done, they both write their serviced interrupt to their claim register, allowing that interrupt to be raised again.

I don’t see a scenario where you can “hang” the system. If CPU1 hangs in the ISR, that only affects the interrupt it was servicing. That interrupt will not be recognised by the PLIC again until the servicing hart writes that the interrupt was handled.