Openocd reset run Error: Timed out waiting for state 1

Archive Freedom E300
1

Should openocd’s “reset run” command work or am I doing something wrong? AFAIK there’s no breakpoint at 0x80000004. Adding “rbp 0x80000004” says there isn’t a breakpoint.

$ work/build/openocd/prefix/bin/openocd -f bsp/env/freedom-e300-hifive1/openocd.cfg -c "reset run"
Open On-Chip Debugger 0.10.0+dev (2017-09-14-17:35)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
adapter speed: 10000 kHz
Info : auto-selecting first available session transport “jtag”. To override use 'transport select '.
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 10000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0x10e31913 (mfg: 0x489 (SiFive, Inc.), part: 0x0e31, ver: 0x1)
Info : [0] Found 2 triggers
halted at 0x80000004 due to software breakpoint
Info : Examined RISCV core; XLEN=32, misa=0x40001105
Info : Listening on port 3333 for gdb connections
Info : JTAG tap: riscv.cpu tap/device found: 0x10e31913 (mfg: 0x489 (SiFive, Inc.), part: 0x0e31, ver: 0x1)
halted at 0x80000004 due to software breakpoint
Error: Timed out waiting for state 1.
in procedure 'reset’
in procedure ‘ocd_bouncer’

2

It won’t work on the HiFive1. It should work on the Coreplex IP Eval FPGA dev kits, and from FPGA images built yourself from https://github.com/sifive/freedom (we haven’t yet released an updated pre-build MCS from that repo).