Multiple Timers

Hi all, I am newbie in RISCV architecture and so SiFive MCUs.
I am using machine timer (mtime) to create and interrupt but I need two more HW timers for different purposes. I would implement something to provide 3 different SW timers, but I need accuracy with a HW Timer.

Just I am trying to understand the FE310 Core (because I may need to change my Arm-Oriented mind). As I see there is no HW Timer Peripheral. Is the mtime only option for all timer needs?
I assume there should not be a limitation in RISCV, just should be about FE310 core. Right?

Yes, the timer support is a function of the SoC not of RISC-V in general.

The FE310 SoC has PWM peripherals that can be used to generate additional hardware timer interrupts.

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I’m not sure why any number of software timers would be less accurate than hardware timers?

The soonest software timer would use the hardware timer.

Certainly there will be a few instructions of latency in deciding what the next setting for the hardware timer should be, but probably no more than a couple of dozen – probably comparable to or less than the saving and restoring of all the registers in the interrupt handler anyway.

Briefly: keep the software timers in an array, structured as a heap, with the soonest timer in the first array element. Use this to set the hardware timer. After the timer is used, if it is periodic then just update its next time and perform a siftDown operation (swap it with the soonest of its two children, if that is before its own updated time, then siftDown from its new location). If the timer was a one-off then replace it with the last active item in the array (making the array 1 shorter), then siftDown.

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I don’t know what device you have in mind, but the FE310-G00X in the HiFive1 boards use a low frequency clock (commonly set at 32.768 Hz, as on the HiFive1) to drive the timer, which works great when you want to get a 1 Hz interrupt for an RTC, but otherwise is a poor choice for anything else due to low precision.

Even getting the typical 1000 Hz scheduler clock in an OS environment is highly inaccurate with a 32.768 Hz input.

Configuring the clock to a higher frequency might be possible, but, being located on the Always-On-Domain, will increase the power usage, making it unsuitable for low-power use cases.

The FE310 is capable of triggering interrupts based on the values in the PWM 16-bit comparator registers, but accuracy is questionable.

Yes, other SoC may have additional timers, but not having a proper system timer defined by the architecture, like the Cortex-M SysTick, is a poor design choice.

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You message would appear to have absolutely nothing to do with mine.

A 32768 Hz clock allows you to get an interrupt within +/- 15 uS of any desired time. This is good enough for many purposes, but obviously inadequate for others.

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Thank you all,

I am trying to run an OS on FE310.
In Arm Architecture, I have been using SysTick Timer for Context Switching timing and two peripheral timers for user needs which process separate queues(heap) to order their user software timers.

I don’t want to change my upper layer implementation to no break the Arm compliance.
Ok, I can implement a HAL Layer Timer implementation using mtimecmp.

Thank you very much.

Good luck with this.

When done, perhaps you can share here your experience, and compare the effort to do the same (scheduler timer, context switching, etc) with Cortex-M.