Make mcs and download a user application problem

Archive Freedom E300
1

Hello,

I have the Artix-7 35T FPGA and I’m following the README of freedom platform github.

To include the user application in .mcs file, I added $(DATAFILE) at the end of the make mcs command as shown below.

<common.mk>
export DATAFILE=$(base_dir)/…/freedom-e-sdk/software/software/demo_gpio/demo_gpio
$(mcs): $(bit)
cd $(BUILD_DIR); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $< $(DATAFILE)

We converted the xip.S file in freedom/bootrom to a hex file and used it as a bootloader.

As a result, a completion message indicating that .bit file was stored at 0x00000000 and user application was stored at 0x00400000 in SPI memory came out.

I downloaded the mcs file to the FPGA using vivado, but the user app did not work.

Honestly, I do not know whether rocket core not working is a problem or user application compile and download process is a problem.

So I looked at the log of make mcs and found six critical warnings.

CRITICAL WARNING: [Vivado 12-1504] The IP is already part of the fileset ‘sources_1’. Requested source ‘/home/moonhg/RISC-V/freedom/builds/e300artydevkit/obj/ip/reset_sys/reset_sys.xci’ will not be added.
CRITICAL WARNING: [Vivado 12-1504] The IP is already part of the fileset ‘sources_1’. Requested source ‘/home/moonhg/RISC-V/freedom/builds/e300artydevkit/obj/ip/ila/ila.xci’ will not be added.
CRITICAL WARNING: [Vivado 12-1504] The IP is already part of the fileset ‘sources_1’. Requested source ‘/home/moonhg/RISC-V/freedom/builds/e300artydevkit/obj/ip/mmcm/mmcm.xci’ will not be added.

CRITICAL WARNING: [Designutils 20-1280] Could not find module ‘ila’. The XDC file /home/moonhg/RISC-V/freedom/builds/e300artydevkit/obj/ip/ila/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module.
INFO: [Timing 38-2] Deriving generated clocks

CRITICAL WARNING: [Designutils 20-1280] Could not find module ‘ila’. The XDC file /home/moonhg/RISC-V/freedom/builds/e300artydevkit/obj/ip/ila/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module.
Parsing XDC File [/home/moonhg/RISC-V/freedom/fpga-shells/xilinx/arty/constraints/arty-master.xdc]

CRITICAL WARNING: [Place 30-722] Terminal ‘qspi_cs’ has IOB constraint set to TRUE, but it is either not connected to a FLOP element or the connected FLOP element could not be brought into the I/O
INFO: [Timing 38-35] Done setting XDC timing constraints.

Could this be the cause of the problem?

How to solve this problem?

Thank you!

2 Likes
2

I guess that your $(DATAFILE) is ELF format file.
You have to change ELF format to binary fromat as following.

riscv64-unknown-elf-objcopy -O binary demo_gpio demo_gpio.bin

We converted the xip.S file in freedom/bootrom to a hex file and used it as a bootloader.

You do not have to convert xip.S. In common.mk, xip.S will be converted to .v file.

romgen := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v
$(romgen): $(verilog)
ifneq ($(BOOTROM_DIR),"")
        $(MAKE) -C $(BOOTROM_DIR) romgen
        mv $(BUILD_DIR)/rom.v $@
endif
1 Like
3

Thank you very much!!!

I solved it!!! lol

4

So, how do we add our own program to the mcs? I don’t follow what needs to include it into the mcs without a programmer.

5

hello,

you can add user application by adding $(DATAFILE) in end of $(mcs) command line at common.mk file

$(DATAFILE) format must be in binary file like below

export DATAFILE=$(base_dir)/…/freedom-e-sdk/software/software/demo_gpio/demo_gpio.bin

1 Like
6

So why is this not part of the instructions and also by default into the make files? I’ve been struggling with this for 2 days now… :sweat_smile: