I have the Xilinx Artix-7 35T Arty FPGA Evaluation Kit and want to run Linux on it. I have found several different possibilities to build a Linux system for spike/qemu, but I do not know how to get it working on the arty board. Is there any short tutorial/readme howto get this working.
Wait … what is this “Z7”. Is there more than one model of Arty?
What I see in stores here is:
Xilinx Artix-35T FPGA (xc7a35ticsg324-1L)
5,200 slices (each slice contains four 6-input LUTs and 8 flip-flops)
I’ve been trying to find out how much of the Arty a HiFive1 emulation takes, but no one seems to know/want to tell. By impression though was that there’d be plenty of space left for an MMU. And DDR3 controller…
Thanks for your question. We previously supported a Linux-capable RISC-V core on Arty (which is what the wordpress article is referring to), but there has been so much progress both in the HW codebase and Linux-land that the project became out of date. The Arty is certainly capable of supporting a Linux-capable core.
Yeah, reading the article, it’s from a year ago and so clearly on the 35T board, not Z7 – which is now $99 not $140. The low end Z7 with far more LUTs is now $140.
Are they compatable? Will any design which works on the older smaller board simply work out of the box on the newer one? i.e. the peripherals need the same interfaces on the FPGA etc
Thank you for your answer Megan.
Is it still possible to get the old sources?
Do you know where I can download the outdated software to run Linux on the Arty 35T?
BTW: Digilent in the meantime has also a 100K variant of the Arty A7, with 249USD a more expensive, but still affordable.
Bur does it really makes sense to run Linux on a ~50 Mhz Core? Only in case you want to change and test the core design. For software development QEMU schould be much faster.
Arty Z7 uses ZYNQ, which uses the same FPGA architecture than ARTIX (structure of CLBs, BRAMs, etc), but ZYNQ has a lot of hard blocks like Gigabit Ethernet, DRAM Controller, two Cortex A9 cores in its „processing system“, and boards like Arty Z7 connect their external hardware (like DRAM ) to these cores.
So when you want to access this hardware from a RISC-V softcore in the FPGA you need a complete different approach.
So basically a design for the Arty A35 will not run on the Z7.
On the other hand I already thought about the idea of running a softcore on a ZYNQ, when you connect it to the AXI ACP port of the processing system it could leverage the large L2 cache normally used for the A9 cores to access the DRAM.