Hi,
We have an SoC based on the U74 core design with 1MB of L2 cache, supporting up to 8GB of DDR.
When using the full 8GB DDR range (0x8_0000_0000–0x9_FFFF_FFFF), it works correctly.
However, when we reduce the DDR to a 4GB configuration (0x8_0000_0000–0x8_FFFF_FFFF), the L2 cache reports the following error:
L2CACHE: DataFail @ 0x00000009.772BAEB0
This error occurs during stress-ng testing with the command:
stress-ng --cpu 4 --timeout 72h --metrics-brief
Each time the error appears, the address is different but always falls after 0x9_0000_0000.
We also observed that the DatECCFailCount counter increments by 4 every time the error occurs.
Does anyone have any suggestions regarding this issue?
Thanks！