L1 cache ECC error injection

HiFive Unleashed
1

Hi,

Does anyone know is there is a way to validate the functionnality of the L1 I$/D$ ECC?
My problem is, I need to check that the L1 ECC is working/reporting correctly at every power-up.
I know it is possible on the L2 cache through the L2 Cache Controller (ECCInjectError register), but apparently there is no such thing for the L1.

(If it is not possible, is there any planned upgrade of the U54-MC for such a feature?)

Thank you !

2

Hi Antonin,

Sorry - there’s no ECC error inject mechanism for the L1 caches and this isn’t planned.
This is a feature that is validated in RTL simulation.

Regards,
Ralph

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