Issue: Error: Target not examined yet


(Naasa Fikri) #1

Follow up to https://github.com/sifive/freedom/issues/127. I have successfully build and uploaded Freedom E300 on my Arty Rev. C board using Vivado 2018.3. OpenOCD can detect the core but when I send telnet command to it, it returns Error: Target not examined yet

nf@ubuntu:~/opt/FreedomStudio/SiFive/riscv-openocd/riscv-openocd-0.10.0-2019.05.1/bin$ ./openocd -f /home/nf/ws/RISCV/freedom-e310-arty-hello/bsp/openocd.cfg 
Open On-Chip Debugger 0.10.0+dev (SiFive OpenOCD 0.10.0-2019.05.1)
Licensed under GNU GPL v2
For bug reports:
	https://github.com/sifive/freedom-tools/issues
adapter speed: 10000 kHz
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
1
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 10000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0x20000913 (mfg: 0x489 (SiFive, Inc.), part: 0x0000, ver: 0x2)
Info : Listening on port 3333 for gdb connections
Info : accepting 'telnet' connection on tcp/4444
Error: Target not examined yet

Any ideas?


(Naasa Fikri) #2

Here is the output with debug enabled

nf<at>ubuntu:~/opt/FreedomStudio/SiFive/riscv-openocd/riscv-openocd-0.10.0-2019.05.1/bin$ ./openocd -f /home/nf/ws/RISCV/freedom-e310-arty-hello/bsp/openocd.cfg -d
Open On-Chip Debugger 0.10.0+dev (SiFive OpenOCD 0.10.0-2019.05.1)
Licensed under GNU GPL v2
For bug reports:
	https://github.com/sifive/freedom-tools/issues
User : 13 1 command.c:544 command_print(): debug_level: 3
Debug: 14 1 options.c:184 add_default_dirs(): bindir=/var/lib/builds/sifive-tools/freedom-tools-qemu-src/obj/x86_64-linux-centos6/install/riscv-openocd-0.10.0-2019.05.1-x86_64-linux-centos6/bin
Debug: 15 1 options.c:185 add_default_dirs(): pkgdatadir=/var/lib/builds/sifive-tools/freedom-tools-qemu-src/obj/x86_64-linux-centos6/install/riscv-openocd-0.10.0-2019.05.1-x86_64-linux-centos6/share/openocd
Debug: 16 1 options.c:186 add_default_dirs(): exepath=/home/nf/opt/FreedomStudio/SiFive/riscv-openocd/riscv-openocd-0.10.0-2019.05.1/bin
Debug: 17 1 options.c:187 add_default_dirs(): bin2data=../share/openocd
Debug: 18 1 configuration.c:42 add_script_search_dir(): adding /home/nf/.openocd
Debug: 19 1 configuration.c:42 add_script_search_dir(): adding /home/nf/opt/FreedomStudio/SiFive/riscv-openocd/riscv-openocd-0.10.0-2019.05.1/bin/../share/openocd/site
Debug: 20 1 configuration.c:42 add_script_search_dir(): adding /home/nf/opt/FreedomStudio/SiFive/riscv-openocd/riscv-openocd-0.10.0-2019.05.1/bin/../share/openocd/scripts
Debug: 21 1 configuration.c:97 find_file(): found /home/nf/ws/RISCV/freedom-e310-arty-hello/bsp/openocd.cfg
Debug: 22 1 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_adapter_khz 10000
Debug: 23 1 command.c:143 script_debug(): command - adapter_khz ocd_adapter_khz 10000
Debug: 25 1 core.c:1645 jtag_config_khz(): handle jtag khz
Debug: 26 1 core.c:1612 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 27 1 core.c:1612 adapter_khz_to_speed(): convert khz to interface specific speed value
User : 28 1 command.c:544 command_print(): adapter speed: 10000 kHz
Debug: 29 1 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_interface ftdi
Debug: 30 1 command.c:143 script_debug(): command - interface ocd_interface ftdi
Debug: 32 1 command.c:364 register_command_handler(): registering 'ocd_ftdi_device_desc'...
Debug: 33 1 command.c:364 register_command_handler(): registering 'ocd_ftdi_serial'...
Debug: 34 1 command.c:364 register_command_handler(): registering 'ocd_ftdi_channel'...
Debug: 35 1 command.c:364 register_command_handler(): registering 'ocd_ftdi_layout_init'...
Debug: 36 1 command.c:364 register_command_handler(): registering 'ocd_ftdi_layout_signal'...
Debug: 37 1 command.c:364 register_command_handler(): registering 'ocd_ftdi_set_signal'...
Debug: 38 1 command.c:364 register_command_handler(): registering 'ocd_ftdi_get_signal'...
Debug: 39 1 command.c:364 register_command_handler(): registering 'ocd_ftdi_vid_pid'...
Debug: 40 1 command.c:364 register_command_handler(): registering 'ocd_ftdi_tdo_sample_edge'...
Debug: 41 1 command.c:364 register_command_handler(): registering 'ocd_ftdi_oscan1_mode'...
Debug: 42 1 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_ftdi_device_desc Olimex OpenOCD JTAG ARM-USB-OCD-H
Debug: 43 1 command.c:143 script_debug(): command - ftdi_device_desc ocd_ftdi_device_desc Olimex OpenOCD JTAG ARM-USB-OCD-H
Debug: 45 1 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_ftdi_vid_pid 0x15ba 0x002b
Debug: 46 1 command.c:143 script_debug(): command - ftdi_vid_pid ocd_ftdi_vid_pid 0x15ba 0x002b
Debug: 48 1 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_ftdi_layout_init 0x0908 0x0b1b
Debug: 49 1 command.c:143 script_debug(): command - ftdi_layout_init ocd_ftdi_layout_init 0x0908 0x0b1b
Debug: 51 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_ftdi_layout_signal nSRST -oe 0x0200
Debug: 52 2 command.c:143 script_debug(): command - ftdi_layout_signal ocd_ftdi_layout_signal nSRST -oe 0x0200
Debug: 54 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_ftdi_layout_signal nTRST -data 0x0100
Debug: 55 2 command.c:143 script_debug(): command - ftdi_layout_signal ocd_ftdi_layout_signal nTRST -data 0x0100
Debug: 57 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_ftdi_layout_signal LED -data 0x0800
Debug: 58 2 command.c:143 script_debug(): command - ftdi_layout_signal ocd_ftdi_layout_signal LED -data 0x0800
Debug: 60 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 61 2 command.c:143 script_debug(): command - ocd_transport ocd_transport select
Info : 62 2 transport.c:286 jim_transport_select(): auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Debug: 63 2 command.c:364 register_command_handler(): registering 'ocd_jtag_flush_queue_sleep'...
Debug: 64 2 command.c:364 register_command_handler(): registering 'ocd_jtag_rclk'...
Debug: 65 2 command.c:364 register_command_handler(): registering 'ocd_jtag_ntrst_delay'...
Debug: 66 2 command.c:364 register_command_handler(): registering 'ocd_jtag_ntrst_assert_width'...
Debug: 67 2 command.c:364 register_command_handler(): registering 'ocd_scan_chain'...
Debug: 68 2 command.c:364 register_command_handler(): registering 'ocd_jtag_reset'...
Debug: 69 2 command.c:364 register_command_handler(): registering 'ocd_runtest'...
Debug: 70 2 command.c:364 register_command_handler(): registering 'ocd_irscan'...
Debug: 71 2 command.c:364 register_command_handler(): registering 'ocd_verify_ircapture'...
Debug: 72 2 command.c:364 register_command_handler(): registering 'ocd_verify_jtag'...
Debug: 73 2 command.c:364 register_command_handler(): registering 'ocd_tms_sequence'...
Debug: 74 2 command.c:364 register_command_handler(): registering 'ocd_wait_srst_deassert'...
Debug: 75 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 76 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 77 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 78 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 79 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 80 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 81 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 82 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 83 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 84 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 85 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 86 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 87 2 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 88 2 command.c:364 register_command_handler(): registering 'ocd_svf'...
Debug: 89 2 command.c:364 register_command_handler(): registering 'ocd_xsvf'...
Debug: 90 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 91 2 command.c:143 script_debug(): command - ocd_transport ocd_transport select
Debug: 92 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_jtag newtap riscv cpu -irlen 5
Debug: 93 2 command.c:143 script_debug(): command - ocd_jtag ocd_jtag newtap riscv cpu -irlen 5
Debug: 94 2 tcl.c:550 jim_newtap_cmd(): Creating New Tap, Chip: riscv, Tap: cpu, Dotted: riscv.cpu, 2 params
Debug: 95 2 tcl.c:574 jim_newtap_cmd(): Processing option: -irlen
Debug: 96 2 core.c:1304 jtag_tap_init(): Created Tap: riscv.cpu <at> abs position 0, irlen 5, capture: 0x1 mask: 0x3
Debug: 97 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_target create riscv.cpu.0 riscv -chain-position riscv.cpu
Debug: 98 2 command.c:143 script_debug(): command - ocd_target ocd_target create riscv.cpu.0 riscv -chain-position riscv.cpu
Debug: 99 2 target.c:1959 target_free_all_working_areas_restore(): freeing all working areas
Debug: 100 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 101 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 102 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 103 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 104 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 105 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 106 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 107 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 108 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 109 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 110 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 111 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 112 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 113 2 command.c:364 register_command_handler(): registering 'ocd_riscv'...
Debug: 114 2 command.c:364 register_command_handler(): registering 'ocd_arm'...
Debug: 115 2 command.c:364 register_command_handler(): registering 'ocd_arm'...
Debug: 116 2 command.c:364 register_command_handler(): registering 'ocd_arm'...
Debug: 117 2 command.c:364 register_command_handler(): registering 'ocd_arm'...
Debug: 118 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 119 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 120 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 121 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 122 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 123 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 124 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 125 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 126 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 127 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 128 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 129 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 130 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 131 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 132 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 133 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 134 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 135 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 136 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 137 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 138 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 139 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 140 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 141 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 142 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 143 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 144 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 145 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 146 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 147 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 148 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 149 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 150 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 151 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 152 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 153 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 154 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 155 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 156 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 157 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 158 2 command.c:364 register_command_handler(): registering 'ocd_riscv.cpu.0'...
Debug: 159 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_riscv.cpu.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
Debug: 160 2 command.c:143 script_debug(): command - ocd_riscv.cpu.0 ocd_riscv.cpu.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
Debug: 161 2 target.c:1959 target_free_all_working_areas_restore(): freeing all working areas
Debug: 162 2 target.c:1959 target_free_all_working_areas_restore(): freeing all working areas
Debug: 163 2 target.c:1959 target_free_all_working_areas_restore(): freeing all working areas
Debug: 164 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_flash bank spi0 fespi 0x20000000 0 0 0 riscv.cpu.0 0x10014000
Debug: 165 2 command.c:143 script_debug(): command - ocd_flash ocd_flash bank spi0 fespi 0x20000000 0 0 0 riscv.cpu.0 0x10014000
Debug: 167 2 fespi.c:147 fespi_flash_bank_command(): fespi_flash_bank_command
Debug: 168 2 fespi.c:164 fespi_flash_bank_command(): ASSUMING FESPI device at ctrl_base = 0x10014000
Debug: 169 2 tcl.c:1156 handle_flash_bank_command(): 'fespi' driver usage field missing
Info : 170 2 server.c:311 add_service(): Listening on port 6666 for tcl connections
Info : 171 2 server.c:311 add_service(): Listening on port 4444 for telnet connections
Debug: 172 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_init
Debug: 173 2 command.c:143 script_debug(): command - init ocd_init
Debug: 175 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_target init
Debug: 176 2 command.c:143 script_debug(): command - ocd_target ocd_target init
Debug: 178 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_target names
Debug: 179 2 command.c:143 script_debug(): command - ocd_target ocd_target names
Debug: 180 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_riscv.cpu.0 cget -event gdb-flash-erase-start
Debug: 181 2 command.c:143 script_debug(): command - ocd_riscv.cpu.0 ocd_riscv.cpu.0 cget -event gdb-flash-erase-start
Debug: 182 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_riscv.cpu.0 configure -event gdb-flash-erase-start reset init
Debug: 183 2 command.c:143 script_debug(): command - ocd_riscv.cpu.0 ocd_riscv.cpu.0 configure -event gdb-flash-erase-start reset init
Debug: 184 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_riscv.cpu.0 cget -event gdb-flash-write-end
Debug: 185 2 command.c:143 script_debug(): command - ocd_riscv.cpu.0 ocd_riscv.cpu.0 cget -event gdb-flash-write-end
Debug: 186 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_riscv.cpu.0 configure -event gdb-flash-write-end reset halt
Debug: 187 3 command.c:143 script_debug(): command - ocd_riscv.cpu.0 ocd_riscv.cpu.0 configure -event gdb-flash-write-end reset halt
Debug: 188 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_riscv.cpu.0 cget -event gdb-attach
Debug: 189 3 command.c:143 script_debug(): command - ocd_riscv.cpu.0 ocd_riscv.cpu.0 cget -event gdb-attach
Debug: 190 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_riscv.cpu.0 configure -event gdb-attach halt
Debug: 191 3 command.c:143 script_debug(): command - ocd_riscv.cpu.0 ocd_riscv.cpu.0 configure -event gdb-attach halt
Debug: 192 3 target.c:1421 handle_target_init_command(): Initializing targets...
Debug: 193 3 riscv.c:423 riscv_init_target(): riscv_init_target()
Debug: 194 3 semihosting_common.c:97 semihosting_common_init():  
Debug: 195 3 command.c:364 register_command_handler(): registering 'ocd_target_request'...
Debug: 196 3 command.c:364 register_command_handler(): registering 'ocd_trace'...
Debug: 197 3 command.c:364 register_command_handler(): registering 'ocd_trace'...
Debug: 198 3 command.c:364 register_command_handler(): registering 'ocd_fast_load_image'...
Debug: 199 3 command.c:364 register_command_handler(): registering 'ocd_fast_load'...
Debug: 200 3 command.c:364 register_command_handler(): registering 'ocd_profile'...
Debug: 201 3 command.c:364 register_command_handler(): registering 'ocd_virt2phys'...
Debug: 202 3 command.c:364 register_command_handler(): registering 'ocd_reg'...
Debug: 203 3 command.c:364 register_command_handler(): registering 'ocd_poll'...
Debug: 204 3 command.c:364 register_command_handler(): registering 'ocd_wait_halt'...
Debug: 205 3 command.c:364 register_command_handler(): registering 'ocd_halt'...
Debug: 206 3 command.c:364 register_command_handler(): registering 'ocd_resume'...
Debug: 207 3 command.c:364 register_command_handler(): registering 'ocd_reset'...
Debug: 208 3 command.c:364 register_command_handler(): registering 'ocd_soft_reset_halt'...
Debug: 209 3 command.c:364 register_command_handler(): registering 'ocd_step'...
Debug: 210 3 command.c:364 register_command_handler(): registering 'ocd_mdd'...
Debug: 211 3 command.c:364 register_command_handler(): registering 'ocd_mdw'...
Debug: 212 3 command.c:364 register_command_handler(): registering 'ocd_mdh'...
Debug: 213 3 command.c:364 register_command_handler(): registering 'ocd_mdb'...
Debug: 214 3 command.c:364 register_command_handler(): registering 'ocd_mwd'...
Debug: 215 3 command.c:364 register_command_handler(): registering 'ocd_mww'...
Debug: 216 3 command.c:364 register_command_handler(): registering 'ocd_mwh'...
Debug: 217 3 command.c:364 register_command_handler(): registering 'ocd_mwb'...
Debug: 218 3 command.c:364 register_command_handler(): registering 'ocd_bp'...
Debug: 219 3 command.c:364 register_command_handler(): registering 'ocd_rbp'...
Debug: 220 3 command.c:364 register_command_handler(): registering 'ocd_wp'...
Debug: 221 3 command.c:364 register_command_handler(): registering 'ocd_rwp'...
Debug: 222 3 command.c:364 register_command_handler(): registering 'ocd_load_image'...
Debug: 223 3 command.c:364 register_command_handler(): registering 'ocd_dump_image'...
Debug: 224 3 command.c:364 register_command_handler(): registering 'ocd_verify_image_checksum'...
Debug: 225 3 command.c:364 register_command_handler(): registering 'ocd_verify_image'...
Debug: 226 3 command.c:364 register_command_handler(): registering 'ocd_test_image'...
Debug: 227 3 command.c:364 register_command_handler(): registering 'ocd_reset_nag'...
Debug: 228 3 command.c:364 register_command_handler(): registering 'ocd_ps'...
Debug: 229 3 command.c:364 register_command_handler(): registering 'ocd_test_mem_access'...
Debug: 230 3 ftdi.c:730 ftdi_initialize(): ftdi interface using shortest path jtag state transitions
Debug: 231 11 mpsse.c:429 mpsse_purge(): -
Debug: 232 12 mpsse.c:710 mpsse_loopback_config(): off
Debug: 233 12 mpsse.c:755 mpsse_set_frequency(): target 10000000 Hz
Debug: 234 12 mpsse.c:747 mpsse_rtck_config(): off
Debug: 235 12 mpsse.c:736 mpsse_divide_by_5_config(): off
Debug: 236 12 mpsse.c:716 mpsse_set_divisor(): 2
Debug: 237 12 mpsse.c:779 mpsse_set_frequency(): actually 10000000 Hz
Debug: 238 12 core.c:1612 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 239 12 core.c:1615 adapter_khz_to_speed(): have interface set up
Debug: 240 12 mpsse.c:755 mpsse_set_frequency(): target 10000000 Hz
Debug: 241 12 mpsse.c:747 mpsse_rtck_config(): off
Debug: 242 12 mpsse.c:736 mpsse_divide_by_5_config(): off
Debug: 243 12 mpsse.c:716 mpsse_set_divisor(): 2
Debug: 244 12 mpsse.c:779 mpsse_set_frequency(): actually 10000000 Hz
Info : 245 12 ftdi.c:358 ftdi_speed(): ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Debug: 246 12 core.c:1612 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 247 12 core.c:1615 adapter_khz_to_speed(): have interface set up
Info : 248 12 core.c:1394 adapter_init(): clock speed 10000 kHz
Debug: 249 12 openocd.c:142 handle_init_command(): Debug Adapter init complete
Debug: 250 12 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport init
Debug: 251 12 command.c:143 script_debug(): command - ocd_transport ocd_transport init
Debug: 253 12 transport.c:239 handle_transport_init(): handle_transport_init
Debug: 254 13 core.c:729 jtag_add_reset(): SRST line released
Debug: 255 13 core.c:753 jtag_add_reset(): TRST line released
Debug: 256 13 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 257 13 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_jtag arp_init
Debug: 258 13 command.c:143 script_debug(): command - ocd_jtag ocd_jtag arp_init
Debug: 259 13 core.c:1407 jtag_init_inner(): Init JTAG chain
Debug: 260 13 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 261 13 core.c:1060 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS
Debug: 262 13 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Info : 263 14 core.c:959 jtag_examine_chain_display(): JTAG tap: riscv.cpu tap/device found: 0x20000913 (mfg: 0x489 (SiFive, Inc.), part: 0x0000, ver: 0x2)
Debug: 264 14 core.c:1190 jtag_validate_ircapture(): IR capture validation scan
Debug: 265 14 core.c:1248 jtag_validate_ircapture(): riscv.cpu: IR capture 0x01
Debug: 266 14 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_dap init
Debug: 267 14 command.c:143 script_debug(): command - ocd_dap ocd_dap init
Debug: 269 14 arm_dap.c:105 dap_init_all(): Initializing all DAPs ...
Debug: 270 14 openocd.c:159 handle_init_command(): Examining targets...
Debug: 271 14 target.c:1609 target_call_event_callbacks(): target event 17 (examine-start) for core 0
Debug: 272 14 riscv.c:958 riscv_examine(): riscv_examine()
Debug: 273 14 riscv.c:395 dtmcontrol_scan(): DTMCONTROL: 0x0 -> 0x5071
Debug: 274 14 riscv.c:968 riscv_examine(): dtmcontrol=0x5071
Debug: 275 14 riscv.c:970 riscv_examine():   version=0x1
Debug: 276 14 riscv-013.c:1723 init_target(): init
Debug: 277 14 riscv-013.c:448 dtmcontrol_scan(): DTMCS: 0x0 -> 0x5071
Debug: 278 14 riscv-013.c:1469 examine(): dtmcontrol=0x5071
Debug: 279 14 riscv-013.c:1470 examine():   dmireset=0
Debug: 280 14 riscv-013.c:1471 examine():   idle=5
Debug: 281 14 riscv-013.c:1472 examine():   dmistat=0
Debug: 282 14 riscv-013.c:1473 examine():   abits=7
Debug: 283 14 riscv-013.c:1474 examine():   version=1
Debug: 284 14 riscv-013.c:259 get_dm(): [0] Allocating new DM
Debug: 285 15 riscv-013.c:393 scan(): 41b 0i w 00000000 <at>10 -> + 00000000 <at>00
Debug: 286 15 riscv-013.c:393 scan(): 41b 0i - 00000000 <at>10 -> + 00000000 <at>00
Debug: 287 15 riscv-013.c:393 scan(): 41b 0i w 00000001 <at>10 -> + 00000000 <at>00
Debug: 288 15 riscv-013.c:404 scan():  dmactive -> 
Debug: 289 16 riscv-013.c:393 scan(): 41b 0i - 00000000 <at>10 -> + 00000000 <at>00
Debug: 290 16 riscv-013.c:393 scan(): 41b 0i w 07ffffc1 <at>10 -> + 00000000 <at>00
Debug: 291 16 riscv-013.c:404 scan():  hasel hartselhi=1023 hartsello=1023 dmactive -> 
Debug: 292 16 riscv-013.c:393 scan(): 41b 0i - 00000000 <at>10 -> + 00000000 <at>00
Debug: 293 16 riscv-013.c:393 scan(): 41b 0i r 00000000 <at>10 -> + 00000000 <at>00
Debug: 294 17 riscv-013.c:393 scan(): 41b 0i - 00000000 <at>10 -> + 03ff0001 <at>10
Debug: 295 17 riscv-013.c:404 scan():  ->  hartsello=1023 dmactive
Debug: 296 17 riscv-013.c:393 scan(): 41b 0i r 00000000 <at>11 -> + 00000000 <at>00
Debug: 297 17 riscv-013.c:393 scan(): 41b 0i - 00000000 <at>11 -> b 00000000 <at>00
Debug: 298 17 riscv-013.c:459 increase_dmi_busy_delay(): dtmcs_idle=5, dmi_busy_delay=1, ac_busy_delay=0
Debug: 299 17 riscv-013.c:448 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x5471
Debug: 300 17 riscv-013.c:393 scan(): 41b 1i - 00000000 <at>11 -> b 00000000 <at>00
Debug: 301 17 riscv-013.c:459 increase_dmi_busy_delay(): dtmcs_idle=5, dmi_busy_delay=2, ac_busy_delay=0
...
Debug: 703 2824 riscv-013.c:448 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x5471
Debug: 705 3096 riscv-013.c:393 scan(): 41b 2180055i - 00000000 <at>11 -> b 00000000 <at>00
Debug: 706 3096 riscv-013.c:459 increase_dmi_busy_delay(): dtmcs_idle=5, dmi_busy_delay=2398061, ac_busy_delay=0
Debug: 707 3097 riscv-013.c:448 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x5471
Debug: 708 3097 openocd.c:161 handle_init_command(): target examination failed
Debug: 709 3097 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_flash init
Debug: 710 3097 command.c:143 script_debug(): command - ocd_flash ocd_flash init
Debug: 712 3097 tcl.c:1222 handle_flash_init_command(): Initializing flash devices...
Debug: 713 3097 command.c:364 register_command_handler(): registering 'ocd_flash'...
Debug: 714 3097 command.c:364 register_command_handler(): registering 'ocd_flash'...
Debug: 715 3097 command.c:364 register_command_handler(): registering 'ocd_flash'...
Debug: 716 3097 command.c:364 register_command_handler(): registering 'ocd_flash'...
Debug: 717 3097 command.c:364 register_command_handler(): registering 'ocd_flash'...
Debug: 718 3097 command.c:364 register_command_handler(): registering 'ocd_flash'...
Debug: 719 3097 command.c:364 register_command_handler(): registering 'ocd_flash'...
Debug: 720 3097 command.c:364 register_command_handler(): registering 'ocd_flash'...
Debug: 721 3097 command.c:364 register_command_handler(): registering 'ocd_flash'...
Debug: 722 3097 command.c:364 register_command_handler(): registering 'ocd_flash'...
Debug: 723 3097 command.c:364 register_command_handler(): registering 'ocd_flash'...
Debug: 724 3097 command.c:364 register_command_handler(): registering 'ocd_flash'...
Debug: 725 3097 command.c:364 register_command_handler(): registering 'ocd_flash'...
Debug: 726 3097 command.c:364 register_command_handler(): registering 'ocd_flash'...
Debug: 727 3097 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_mflash init
Debug: 728 3097 command.c:143 script_debug(): command - ocd_mflash ocd_mflash init
Debug: 730 3097 mflash.c:1377 handle_mflash_init_command(): Initializing mflash devices...
Debug: 731 3097 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_nand init
Debug: 732 3097 command.c:143 script_debug(): command - ocd_nand ocd_nand init
Debug: 734 3097 tcl.c:497 handle_nand_init_command(): Initializing NAND devices...
Debug: 735 3097 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_pld init
Debug: 736 3097 command.c:143 script_debug(): command - ocd_pld ocd_pld init
Debug: 738 3097 pld.c:205 handle_pld_init_command(): Initializing PLDs...
Debug: 739 3097 gdb_server.c:3425 gdb_target_start(): starting gdb server for riscv.cpu.0 on 3333
Info : 740 3097 server.c:311 add_service(): Listening on port 3333 for gdb connections

(Erik Danie) #3

The message you shared looks like normal openocd operation. Its last message is it waiting for a gdb connection.

What are you trying to do with your telnet connection? Could you try doing the same on a gdb connection and seeing if that works?


(Naasa Fikri) #4

I use telnet because gdb would not let me connect. Here is the snippet after gdb tried to connect. I call gdb from Freedom Studio and run OpenOCD manually.

Debug: 725 2169 gdb_server.c:3425 gdb_target_start(): starting gdb server for riscv.cpu.0 on 3333
Info : 726 2169 server.c:311 add_service(): Listening on port 3333 for gdb connections
Info : 727 79088 server.c:100 add_connection(): accepting 'gdb' connection on tcp/3333
Debug: 728 79089 breakpoints.c:358 breakpoint_clear_target_internal(): Delete all breakpoints for target: riscv.cpu.0
Debug: 729 79089 breakpoints.c:543 watchpoint_clear_target(): Delete all watchpoints for target: riscv.cpu.0
Debug: 730 79089 target.c:1609 target_call_event_callbacks(): target event 19 (gdb-attach) for core 0
Debug: 731 79089 target.c:4569 target_handle_event(): target(0): riscv.cpu.0 (riscv) event: 19 (gdb-attach) action: halt
Debug: 732 79089 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_halt
Debug: 733 79089 command.c:143 script_debug(): command - halt ocd_halt
Debug: 735 79089 target.c:3059 handle_halt_command(): -
Error: 736 79089 target.c:573 target_halt(): Target not examined yet
Debug: 737 79089 command.c:651 run_command(): Command 'halt' failed with error code -4
User : 738 79089 command.c:544 command_print(): 
Debug: 739 79089 fespi.c:942 fespi_probe(): Assuming FESPI as specified at address 0x10014000 with ctrl at 0x20000000
Error: 740 79089 target.c:2457 target_write_u32(): Target not examined yet
Error: 741 79089 fespi.c:192 fespi_write_reg(): fespi_write_reg() error writing 0x1 to 0x10014050
Error: 742 79089 core.c:263 get_flash_bank_by_num(): auto_probe failed
Error: 743 79089 gdb_server.c:1006 gdb_new_connection(): Connect failed. Consider setting up a gdb-attach event for the target to prepare target for GDB connect, or use 'gdb_memory_map disable'.
Error: 744 79089 server.c:104 add_connection(): attempted 'gdb' connection rejected

(Erik Danie) #5

I bet the issue has to do with a misaligned .cfg file. Can you attach the .cfg file that you are using to connect OpenOCD, as well as the dts?


(Naasa Fikri) #6

Here they are. They are generated by FreedomSDK. except the .cfg file which I modified slightly to match my adapter. I also commented the halt command to prevent the OpenOCD from exiting. halt will result in Error: Target not examined yet

dts:

/dts-v1/;

/ {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "sifive,freedom-e310-arty";
        model = "sifive,freedom-e310-arty";

        chosen {
                stdout-path = "/soc/serial@10013000:115200";
                metal,entry = <&sip0 0x400000>;
        };

        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "sifive,fe310-g000";
                L6: cpu@0 {
                        clocks = <&hfclk>;
                        compatible = "sifive,rocket0", "riscv";
                        device_type = "cpu";
                        i-cache-block-size = <64>;
                        i-cache-sets = <128>;
                        i-cache-size = <16384>;
                        next-level-cache = <&sip0>;
                        reg = <0>;
                        riscv,isa = "rv32imac";
                        sifive,dtim = <&dtim>;
                        sifive,itim = <&itim>;
                        status = "okay";
                        timebase-frequency = <1000000>;
                        hardware-exec-breakpoint-count = <4>;
                        hlic: interrupt-controller {
                                #interrupt-cells = <1>;
                                compatible = "riscv,cpu-intc";
                                interrupt-controller;
                        };
                };
        };

        soc {
                #address-cells = <1>;
                #size-cells = <1>;
                #clock-cells = <1>;
                compatible = "sifive,freedom-e310-arty";
                ranges;

                hfclk: clock@0 {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
                        clock-frequency = <65000000>;
                };

                clint: clint@2000000 {
                        compatible = "riscv,clint0";
                        interrupts-extended = <&hlic 3 &hlic 7>;
                        reg = <0x2000000 0x10000>;
                        reg-names = "control";
                };
                local-external-interrupts-0 {
                        compatible = "sifive,local-external-interrupts0";
                        interrupt-parent = <&hlic>;
                        interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
                };
                plic: interrupt-controller@c000000 {
                        #interrupt-cells = <1>;
                        compatible = "riscv,plic0";
                        interrupt-controller;
                        interrupts-extended = <&hlic 11>;
                        reg = <0xc000000 0x4000000>;
                        reg-names = "control";
                        riscv,max-priority = <7>;
                        riscv,ndev = <26>;
                };
                global-external-interrupts {
                        compatile = "sifive,global-external-interrupts0";
                        interrupt-parent = <&plic>;
                        interrupts = <1 2 3 4>;
                };

                debug-controller@0 {
                        compatible = "sifive,debug-011", "riscv,debug-011";
                        interrupts-extended = <&hlic 65535>;
                        reg = <0x0 0x100>;
                        reg-names = "control";
                };

                maskrom@1000 {
                        reg = <0x1000 0x2000>;
                        reg-names = "mem";
                };
                otp@20000 {
                        reg = <0x20000 0x2000 0x10010000 0x1000>;
                        reg-names = "mem", "control";
                };

                dtim: dtim@80000000 {
                        compatible = "sifive,dtim0";
                        reg = <0x80000000 0x4000>;
                        reg-names = "mem";
                };
                itim: itim@8000000 {
                        compatible = "sifive,itim0";
                        reg = <0x8000000 0x4000>;
                        reg-names = "mem";
                };

                pwm@10015000 {
                        compatible = "sifive,pwm0";
                        interrupt-parent = <&plic>;
                        interrupts = <23 24 25 26>;
                        reg = <0x10015000 0x1000>;
                        reg-names = "control";
                };
                gpio0: gpio@10012000 {
                        compatible = "sifive,gpio0";
                        interrupt-parent = <&plic>;
                        interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>;
                        reg = <0x10012000 0x1000>;
                        reg-names = "control";
                };
                uart0: serial@10013000 {
                        compatible = "sifive,uart0";
                        interrupt-parent = <&plic>;
                        interrupts = <5>;
                        reg = <0x10013000 0x1000>;
                        reg-names = "control";
                        clocks = <&hfclk>;
                        pinmux = <&gpio0 0x30000 0x30000>;
                };
                sip0: spi@10014000 {
                        compatible = "sifive,spi0";
                        interrupt-parent = <&plic>;
                        interrupts = <6>;
                        reg = <0x10014000 0x1000 0x20000000 0x20000000>;
                        reg-names = "control", "mem";
                };
        };
};

cfg:

#write_config_file
# JTAG adapter setup
adapter_khz     10000

#source [find interface/olimex-arm-usb-ocd.cfg]

interface ftdi
ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-OCD-H"
ftdi_vid_pid 0x15ba 0x002b

ftdi_layout_init 0x0908 0x0b1b
ftdi_layout_signal nSRST -oe 0x0200
ftdi_layout_signal nTRST -data 0x0100
ftdi_layout_signal LED -data 0x0800

set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1

flash bank spi0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10014000
#init

if {[ info exists pulse_srst]} {
	ftdi_set_signal nSRST 0
	ftdi_set_signal nSRST z
sleep 1500
}
#halt

#flash protect 0 64 last off
#echo "Ready for Remote Connections"

(Erik Danie) #7

So it seems like something is wrong with the spi flash device communication, though the address mapping of the dts is in line with what the cfg is trying to access. One possibility is that somehow the fpga bitstream pin constraints are incorrect. What particular fpga board are you using? The freedom-e310 is targeted for an Arty 35T, the 100T might be slightly different pin names.

In the meantime, if you just want to get something working and don’t care about the spi flash chip, you can comment out this line in the cfg file (add a “#” before the line) and I think you should be able to communicate over gdb:

flash bank spi0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10014000

(Naasa Fikri) #8

Still no luck. It stops on halt. I also tried it with 2 different Arty 35T boards, Rev C (with Micron n25q128-3.3v flash) and Rev E (with Spansion S25FL128SAGMF100 flash) and the same issue persist. Do you know where I can find the already built MCS file from SiFive? I will try to compare it with the one I built.


(Yuhong Fu) #9

https://sifive.cdn.prismic.io/sifive%2F7e2ff9cf-23e2-443c-a4cb-ffc5903e9b59_freedom-e310-arty-1-0-2.mcs.zip
You can check this one