How to disable C extension in RISC-V compiler

Archive RISC-V
1

I have segger embedded studio for RISC-V. I want to disable C extension in RISC-V compiler. But i dont know how can i do that?

Any idea is welcomed

2

To compile without the C extension, specify a -march option without the C extension. If you are currently compiling for -march=rv32imac then compile for -march=rv32ima to get the same code without the C extension.

That tells the compiler to stop generating C instructions, but your precompiled libraries may still be using the C extension. The compiler has multilib support, so it has libraries built with multiple march and mabi values, but we don’t have a complete set as there are a lot of possible combinations. I don’t think that rv32ima is one of the current ones, but rv32im is so you could try that instead if you don’t need the A extension. You can see the set of libraries by passing the --print-multi-lib option to gcc.

If writing assembly language code, you can turn of the C extension with “.option norvc” and can turn it on with “.option rvc”. You can also use “.option push” before changing a setting, and then use “.option pop” later to restore the original settings.

1 Like