RISC-V assembly code without pseudo instructions

I am able to generate risc-v assembly code using -S but it also contains many pseudo instructions and assembler directives. This file is supposed to go into the linker that generate object code. Is there any way to generate assembly code without any pseudo instructions and assembler directives? Is there any tool that converts assembly with pseudo instructions to raw assembly that contains only ISA instructions?

You can’t generate proper RISC-V ELF object files without some assembler directives. The -mexplicit-relocs option will avoid some of the pseudo instructions, but not all of them. There is no way to avoid all of the pseudo instructions in the compiler output. GCC emits assembler code that is expected to be passed through GNU as to form object files, which then get passed to the linker. You could try disassembling object files to get raw instructions, but that is likely to be awkward. Objdump -dr on an object file will generate raw assembly instructions and the associated relocations. It isn’t clear why you need or want raw assembly.

Hi Jim,
Actually, I have figured out some assembly code optimization techniques that can be applied on raw assembly. That’s why , I need to know about a tool that converts the assembly file to raw assembly. Basically, I want the output of linker in terms of raw assembly which then converts to machine code.

If you want the output of the linker then use the output of the linker :slight_smile:

riscv64-unknown-elf-gcc -O hello.c -o hello
riscv64-unknown-elf-objdump -d -M no-aliases hello

You might also like to check out my blog on an open Arty RISC-V computer I’m developing called the ‘ArtyRV board’ (see http://lavaworkshop.tumblr.com).

The project includes an interactive RISC-V disassembler, which is built right in to the ‘RVStudio’ IDE. Currently the disassembler loads in and disassembles RV32I binary and coe files, but will soon handle Intel hex (and probably elf) files as well. The disassembled output can be saved out as a clean ASM source code file, ready for you to put in whatever assembly directives you want, and then use however you like.

There are some screencaps in the blog (see part 7) showing the output of the RISC-V disassembler.

If you need any features added or have comments, please feel free to message or email me.

Blog sections include:

  • Summary
  • Introduction
  • Finding a RISC-V core for the Arty
  • Getting the RISC-V core running
  • Designing a VGA video controller
  • The beauty of bare metal RISC-V
  • An interactive RISC-V disassembler
  • Programming the ArtyRV board in C
  • RVStudio gets a powerful IDE
  • Where do we go from here?