True @bsvtgc while AON is where the various sorts of resets happen, they are sensed and reported in the sub-block of the PMU. This is presumably done so that basic functions of an analog nature (clock timings and voltage levels) come alive before any digital I/O (CPU, bus activity, etc) is engaged.
Think of AON as a “container” of other sub-blocks, of which there are six: WDOG, RTC, LFR, BackupRegs, PMU, and the AON itself. All of these six sub-blocks reside at the AON base address 0x1000 0000.
The PMU sub-block, for example, is configured with offsets 0x100 thru 0x14c.
Thus, the PMU diagram of Figure 8 of Chapter 15, and it’s register map in Table 37, fits nicely in the bigger picture inside the greater AON diagram of Figure 6 of Chapter 13, and its overall register map in Table 34.
You can see the actual circuit of the greater AON Block circuit diagram in its Scala documentation. You are right, I cannot find any mention of its aoncfg register (at offset 0x300); or for that matter, the bandgap measurement register, either.
The riscv-reset-path.png figure (in earlier message) shows how, on the HiFive board, an analog ERST input to the AON reset circuitry becomes a digital PMU_OUT_0 signal from the PMU sub-block.
Notice an interesting thing, that both of the internally sourced ring oscillators, HFR and LFR, are very similar in their construction – only their design parameters (i.e., number of inverter gates in their chains, and the propagation delays of each of those gates) are different, hence giving their different frequency ranges: KHz for the LFR, and MHz for the HFR. However, the LFR is at offset 0x7C of the AON’s base of 0x1000 0000, while the HFR is at offset 0x00 of the PRCI’s base of 0x1000 8000. This is noted in the PRCI chapter where LFR is described but referred later to the AON Chapter. This has always bothered me, it makes it difficult to organize the generic ring oscillator code stretched between two blocks and sub-blocks in an object-oriented way.
Those specific design parameters experimentally determined to be
HFR : a=11.558, b=35 (PRCI block base 0x1000 8000)
LFR : a=8.728, b=31 (AON block base 0x1000 0000)
with frequency of the ring oscillator defined given by the following equation
Hz = 1 / (a * (1 - (trim - 16)/b))
Where ‘trim’ is the five-bit value from 0 to 31 expressed as signed 2’s complement from -16 to +15.
A suggestion for a complete state machine model is shown in the prci.s file of my github repo at Demonstrating PRCI. There’s a tiny bug in my block diagram that I have not yet redrawn: the PLL post divider ‘d’ term is actually after the ‘pllbypass’ mux, not before it; and changing the value of ‘d’ does not in any way affect the state of PLL lock. You can think about ‘d’ and ‘outdiv’ together in the same sense.