@bsvtgc Table 42 of the Manual is a little bit unclear in this regard.
This table describes the ‘pmucause’ register, at offset 0x144.
The ‘pmucause’ field, which should actually be called ‘wakeupcause’, only applies to bits [2:0], and is further described in detail by detail Table 43.
The ‘resetcause’ field which is not shown (by mistake?) in Table 42, applies to bits [10:8], and is further described in detail by Table 44 – except for the first three lines which are a redundant copy/paste from the bits of the ‘wakeupcause’ field above.
All other bits of the ‘pmucause’ register, [7:3] and [31:11], are ‘reserved’ and unused.
Updated Tables 42, 43, and 44 of Chapter 15 of the Power Management Unit (PMU) are shown below.
Thus, to answer your question, the first (least significant) three bits of the ‘pmucause’ register tell what event woke up the chip. In the case of a reset event, shown by bit [0] being “H”, the higher-order bits (i.e., bits [10:8] of the ‘resetcause’ field) tell you whether it was a power-on event, External low-going pulse on the “ERST” pin (i.e. the reset button), or the watchdog got hungry.
Note that in case of wakeup from RTC (real time clock) or dwakeup, those three bits of the ‘resetcause’ field do not apply.
How to handle Reset::PowerOn or Reset::External is entirely up to how you arrange the wakeup and sleep program state machines in the PMU. By default (actually the Flash Recovery Mechanism program in OTP memory) the External Reset event generates a brief negative going pulse on the one of the two PMU signal pins – PMU_OUT_0 – for the purpose of completely unpowering the CPU core’s 1V8 supply.
With the Hi Five and also Lo Five boards the External mode of reset gives barely enough low-active time to completely power-off (i.e., disable) the VDD_1V8 regulator and thus completely reset the chip. This has to do with the very long 100K Ohm and 1 uF time constant and the voltage regulator’s input boas current on its digital control input Enable pin. This is talked about in the discussion of understanding the PRCI Clock Path and how reset handles the combination of the AON and PMU blocks and thus generates the PMU_OUT_0 signal to control power on/off in a less physical (than unplugging) way.