FE310-G000 dminfo openocd

I have a breakout board with one of these parts on it, and am trying to get into the part via jtag via openocd.

interface ftdi
ftdi_vid_pid 0x0403 0x6014
ftdi_layout_init 0x0008 0x00fb

#D0 TCK
#D1 TDI
#D2 TDO
#D3 TMS

adapter_khz 10000
telnet_port 4444
gdb_port 0
tcl_port 0

set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1

#flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME
#flash protect 0 64 last off

using an adafruit FT232H breakout. making progress as others have but I dont see an answer to the problem.

Open On-Chip Debugger 0.10.0+dev-00382-g5d9f486 (2018-06-19-19:02)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
adapter speed: 10000 kHz
Info : auto-selecting first available session transport “jtag”. To override use 'transport select '.
1
Info : Listening on port 39839 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 10000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0x10e31913 (mfg: 0x489 (SiFive, Inc.), part: 0x0e31, ver: 0x1)
Error: OpenOCD only supports Debug Module version 1, not 0 (dminfo=0x0)
Info : Listening on port 42117 for gdb connections

and of course then

telnet localhost 4444
Trying 127.0.0.1…
Connected to localhost.
Escape character is ‘^]’.
Open On-Chip Debugger

halt
Target not examined yet

How do I/we get past this error:

Error: OpenOCD only supports Debug Module version 1, not 0 (dminfo=0x0)

Is it an openocd thing is it a chip configuration thing do I need to strap the pins differently? What am I missing?

Are you inadvertently controlling the System Reset pin as well, or did you really only connect the 4 JTAG pins you mentioned? Most JTAG connectors also include a system reset (and sometimes TRST, which doesn’t matter) connection.

It looks like your chip is being held in reset.

I can use a reset from the ftdi, but have historically never needed it to do jtag. It would need to connect to something on the chip which I tend to control separately.

I have AON ERST N strapped high, deasserted. but have pulled it either way with no change in results. I do not see another reset in the datasheet, am I missing one?

I did not provide an external clock to the device, there is an internal clock, I do not need an external clock correct?

Is there a minimal reference design, the minimum you need to get the part working? No crystal/clock no spi flash, etc? Power, caps, jtag?

Thanks,
David