External Debugger with HiFive1 Rev B

I want to use Segger JLink Ultra debug probe to debug HiFive1 Rev B. The board has Segger OB which seems to interfere with the external debugger. I contacted Segger and I was told that there is no non-intrusive way to use an external probe with this board - SiFive HiFive1 - SEGGER Wiki.

I am looking for an intrusive way to be able to use external probe. I tried to connect TP4 to GND to hold the Segger OB in reset but that does not seem to work. Does anyone know a way to use an external debug probe? Would de-soldering R24, R25 and R26 help?


Hi @aggarg Gautav, welcome! That’s an excellent question.

Great idea to use TP4 (schematic on sheet 4, U3-34, DBG_RST), and hold TP4 low, so that U3 might keep all of its I/O lines as inputs or otherwise floating states without disturbing the target FE310 chip. Apparently this was not the case.

Did you try not connecting the micro-usb cable at J5? If U3 doesn’t see any USB activity, it might go to a dormant or sleeping state and also float its outputs.

Removing R24, R25, and R26 is probably not enough; you would most likely have to separate the JTAG_SRST line by cutting the trace from U3-64 (hoping there’s no via underneath U3). Unfortunately, HiFive has no easy series resistor on the JTAG_SRST line to remove.

The TP4 signal is also available at J9-3, which is a really neat set of test points for use with a quick connect pogo pin cable such as tag-connect

To see how U3 handles its DBG_RST input, check with a scope on its output lines DBG_TGT_TDI, _TCK, and _TMS. This might give a clue of U3’s various states of operation. Hopefully, you can find some mode or perhaps even unmentioned input pin which keeps the PTD7 output (JTAG_SRST) in a floating state, and not similarly pulled low.

Also interesting is this reference: Segger, JLink, and the U3 (MK22FN128VLH10)