E21 RTL bring up for JTAG interface

Hi @knfrey great question! I’m not at all familiar with RTL but your observation Error: Target not examined yet intrigues me. It is the same I’ve seen many times with my hardware asic SoC, the FE310-G002.

What is your openocd setup and configuration (tcl)? You can see how I do things in the fe310-g002.cfg file of RISC Five Easy As PI. More detail is in Demystifying OpenOCD

Are you using a USB JTAG device with the FT(2)232 chip? There’s a little trouble I found which I describe in fixing the FT chip glitch. It relates to the default configuration of the FT chip pin states.

Some other relevant discussions are here in the forums at Dmcontrol_stuck_in_infinite_loop and Understanding the PRCI clock path.