Datapath behavior for consecutive loads/stores

benjaminou4412 (Benjamin Ou) June 20, 2019, 8:41pm 1

How does the datapath handle a case where we have consecutive memory accesses and say, a cache miss occurs causing a long memory access stage? Is it implementation-dependent, or is the behavior in this case somehow standarized?

Topic		Replies	Views
Must the following instruction wait for completion of a memory load ？ SiFive RISC-V Core IP Evaluation	3	2068	December 29, 2018
The load-reserved and store-conditional instructions are only supported on cached regions Freedom U500	2	2144	June 2, 2019
Behaviour of instruction cache next-line prefetcher HiFive1 Rev B	6	1803	December 12, 2020
Does I-Cache Miss Stall CPU Interrupt Recognition? HiFive1 Rev B	3	2484	November 30, 2017
Ask help: where to get accurate cycle number of each instruction on a specific RISC-V core? SiFive RISC-V Core IP Evaluation	3	2611	December 29, 2018

Datapath behavior for consecutive loads/stores

Related Topics