Hi Everyone, I hope this is the right place to put this. It’s either here or the Freedom Unleashed forum and I’m not 100% sure which one would be better. I’ll preface this by saying I’m much more used to working on much less complex boards - that will probably become more obvious in a minute.
Anyways, I’ve modified U-Boot to perform a verified boot using RSA 2048 and I’m printing out cycle counts for the actual verification step and I’m seeing a number that doesn’t totally make sense to me. Here’s the code in rsa_verify_with_keynode located in rsa-verify.c:
printf("Verifying signature......."); #ifndef _GNU_SOURCE //This is int here, but I've tried unsigned long, unsigned long long, uint64_t, etc including changing the appropriate printf formatter below int t, t1; t = rdcycle(); #endif ret = rsa_verify_key(&prop, sig, sig_len, hash, info->crypto->key_len, info->checksum); #ifndef _GNU_SOURCE t1 = rdcycle(); printf("Successfully verified signature?? %d\n", t1 - t); #endif
So I’m getting a cycle count out of this RSA verification of 8,973,663 cycles and I know that when I run RSA 2048 verification on an arm cortex m4 device I hover around 3,500,000 cycles so something is up. This number is also pretty consistent, so its at least reliably high.
As a test I chained together 100 asm(“nop”) calls and got a cycle count of somewhere around ~800 - ~1000.
So what am I missing? Am I accessing the cycle counter incorrectly? Are interrupts causing an inflated cycle count? If so, can I turn off interrupts? bootm_disable_interrupts() doesn’t appear to have any effect and disable_interrupts() in HiFive_UBoot/arch/riscv/lib/interrupts.c is literally just a return statement.