Core IP simulation issue on synopsys VCS

Archive SiFive RISC-V Core IP Evaluation
1

Hi

I got E20 Evaluation IP from Core Designer at SiFive Homepage.
And tried to run testbench via VCS simulatior.

When I type a command below, it displays an error.
make all-vcs

Error-[SVA-SSTINSC] SVA-system task in non-SVA context.
Attempt to use a SVA-system task in non-SVA context.
“rtl/testbench/CoreIPSubsystemAllPortRAMTestHarness.sv”, 2635: $fatal;

Anyone can solve this problem?
(VCS version is 2009. Does that cause the problem?)

thanks.

2

Well, I found alternative way to process the simulation.

  1. Delete or comment out all ‘$fatal’ syntax

    • Tool was right. $fatal syntax can be operated in ‘assert’ condition loop, not ‘if’ condition loop.
    • I assume that VCS upper K-2015.09-SP2 version can understand SVA syntax in ‘if’ condition loop. Please reply if i was wrong

  2. comment out ‘-debug_access+pp’ and add ‘-debug_pp’ option to ‘vcs’ command in Makefile

  3. comment out line 82 in ‘rtl/testbench/TestFinisher.sv’

But it is not exact soultion i think

3

Yes with ‘newer’ version like 2015.09 it will compile out of the box.