Convert code scala to RTL in Sifive-Blocks

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1

Hi All,
I want to generate code scala Sifive-Blocks/src/main/scala/devices/pwm to Verilog. I am beginning learn language scala. And I am also know how to Sifive-Blocks work because there is no readme.md

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I’m not a hardware guy, but would suggest looking at sifive/freedom which includes sifive/sifive-blocks, and does have a README.md that mentions how to generate verilog.