Hi. Does RISC-V incorporate a barrel shifter?
I did not see it in the riscv_specv2.2.
The RISC-V base integer ISA has instructions to shift a register left or right by a number of bit positions specified by a literal in the instruction or by the contents of a register.
I don’t think any constraint is placed on the implementation of shifts. A conforming implementation could shift by one bit per clock cycle until the specified shift amount had been achieved.
In practice, I’m not aware of any RISC-V implementations without fast (single-cycle) shifts by arbitrary amounts. Certainly not any current SiFive processor.
And compilers assume they can quickly sign-extend or zero-extend a value with a left shift followed by an arithmetic or logical right shift.
1 Like
Hi, you said:
Is this statement correct? It looks like a double negative.
SLLI/SRLI looks like it will do the shifting you describe.
Actually I need very fast rotation for encryption.
thanks…dd
Yes, it is correct. All RISC-V implementations I’m aware of have fast shifters.
Rotations will be available in the future “B extension”. I don’t believe the E310 or U540 support the B extension. So you’ll have to use SLL and SRL, and then OR the results together.
BlueSpec has one with the option of serial shifts :
However, the make files default to shifters that finish in a single cycle:
ok thx