A problem of the reset signal

I try to run the Freedom E300 on my FPGA, but fail. The SoC has been downloaded into the FPGA successfully, but it can not run.

Then I run the simulation in Vivado, and find that a signal named “sys_reset” is always high, which makes the system always in reset state. The detail is as follows.

In the file “freedom/src/main/scala/everywhere/e300artydevkit/Platform.scala”, the reset signal of “sys.reset” is provided by “sys.aon.rsts.corerst”. The “sys.reset” is the reset signal of module E300ArtyDevKitSystem.
class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module {
val sys = Module(LazyModule(new E300ArtyDevKitSystem).module)
val io = new E300ArtyDevKitPlatformIO

val async_corerst = sys.aon.rsts.corers

Then I find the signal of “sys.aon.rsts.corerst” in the file “sifive-blocks/src/main/scala/devices/mockaon/MockAONWrapper.scala” (in line 80)
io.rsts.corerst := aon_io.moff.corerst

It seems that “aon_io.moff.corerst” and “io.rsts.corerst” are the same signal.
From the source I can not find when the signal “corerst” can be released.