If you’re planning to attend the 7th RISC-V Workshop hosted by Western Digital next week (Nov. 28-30) please look for us on the agenda. SiFive and our partners have a number of presentations planned, starting with the RISC-V State of the Union given by co-founder Krste Asanovic at 9 a.m. on Tuesday!
Other SiFive presentations to look for include:
• RISC-V Hypervisor Extensions by Andrew Waterman (9:42 a.m., Nov. 28)
• Freedom U500, a Linux-Capable, 1.5GHz Quad-Core RV64GC Based SoC by Jack Kang (12:24 p.m., Nov. 28)
• TileLink: A Free and Open-Source, High-Performance Scalable Cache-Coherent Fabric Designed for RISC-V by Wesley Terpstra (11:54 a.m. Nov. 29)
Announced partner talks include (other surprises coming…)
• RISC-V Debug Support by Lauterbach TRACE32 by Bob Kupyn of Lauterach (2:48pm, Nov 28)
• J-Link – professional debug probe now available for RISC-V by Paul Curtis of Segger (3:00pm, Nov 28)
• Boosting RISC-V ISA with Open Source Peripherals: An SoC for Low Power Sensors by Elkim Roa of OnChip (11:30am, Nov 29)
We’re excited to see everyone again since so much has happened in the community since the previous Workshop. If you’re there, please come find us and tell us how you’re working with RISC-V. We’ll be there both days as well as during the networking reception. We hope to see you there!