In the instruction lay-out of RISC-V, why adding the S-type instruction ?
Since in old RISC consists of only R-type I-type and J-type, I am just wondering the specialty of this layout instruction.
To avoid moving register specifiers around, which are more critical in decode.
"Old RISC"s, such as SPUR (aka RISC-IV), made similar decision.
Excuse me, Krste ,
Do you mean that with all register specifier in their fixed position would make the decoder faster and smaller ?
But simply using old I-type for Store Instruction , would that have any disadvantage for that ?
Yes, it’s faster this way. Using I-type for stores would be worse.
Get it ! Thanks for your reply Krste